[en] An existing cross-assembler with macro-option was modified to allow the usage of the ZEUS macros. The ZEUS macros are understood by the assembler without prior definition by the user. ZEUS macros allow the programmer, who is obliged to code his TPA (PDP-8) programs on the assembler level to formulate his program logic as in a higher level language. ZEUS macros offer all basic elements necessary for structured programming. (author)

[en] Parameters of the muon spectrometer of the tagged neutrinos facility constructed in IHEP for measuring momentum and sihn of muon charge produced in neutrino interactions are presented. Spectrometer is composed of eight magnetized disks 5 m in-diameter and 25 cm thick interleaved with coordinate planes. Each disk has a winding providing for magnetic field intensity within 1.5-1.9 T. Charged particle coordinates are determined by measuring drift time in drift tubes. 80/20% argon-methane mixture is a working gas. Total tube volume is 30 m³. Flowsheet of readout system and characteristics of drift tubes are presented. 7 figs

[en] A method is proposed to recognize and resolve double-hit structures in 100 MHz FADC pulses using data taken with prototypes of the cylindrical outer z chamber of the HERA detector H1. With 90% efficiency double hits can be resolved down to distances of about 2.5 mm. The peak position of the second pulse can be reconstructed by subtracting a reference pulse from the signal which is derived from the data themselves. The resolution for perpendicular track crossing is about 250 μm. The method is fast and can be extended to multiple hits (n>2). (orig.)

[en] We describe a proposal to upgrade the existing H1 tracking detector by a semiconductor backward tracking telescope consisting of 8 beam concentric discs to measure the gluon and quark distribution functions at very low Bjorken x. Each disc comprises 3 planes of strip and pad Silicon detectors made of 4' wafers in order to determine the polar angle, the transverse momentum and to trigger on deep inelastically scattered electrons. The paper details the simulation work and the layout constraints on the semiconductors and it reviews the technical and electronics design of the trigger which has to cope with very high beam background rates and the HERA bunch crossing rate of 10.4 MHz. A first phase of the project was approved by the H1 collaboration and will be operational in 1994. (orig.)

[en] Test measurements were performed with prototypes (full-scale radius and single cells) of the outer z-drift chamber (COZ) of the central tracker of the HERA experiment H1. The COZ consists of a 2.20 m long cylindrical arrangement of rectangular drift cells made of 24 identical rings of 47 cm radius with sense wires strung in a 24-fold polygon around the beam axis. The signals are transmitted via flexible twin lines to the preamplifiers located outside the gas volume at the end flanges. The tests were performed at a DESY test beam using Ar/CH₄ and Ar/C₃H₈ and a 100 MHz FADC readout. Detailed results on the geometric efficiency, resolution and charge division are reported. (orig.)

[en] The authors describe a proposal to upgrade the existing H1 tracking detector by a semiconductor backward tracking telescope consisting of 8 beam concentric discs to measure the gluon and quark distribution functions at very low Bjorken x. Each disc comprises 3 planes of strip and pad silicon detectors made of 4 inch wafers in order to determine the polar angle, the transverse momentum and to trigger on deep inelastically scattered electrons. The paper details the simulation work and the layout constraints on the semiconductors. It reviews the technical and electronics design of the trigger which has to cope with very high beam background rates and the HERA bunch crossing rate of 10.4MHz. A first phase of the project was approved by the H1 collaboration and will be operational in 1994

[en] CTA (Cherenkov Telescope Array) is an initiative to build the next generation ground-based γ-ray instrument. The CTA array will allow studies in the very-high-energy domain in the range from a few tens of GeV to more than a hundred TeV, extending the existing energy coverage and increasing by a factor 10 the sensitivity compared to current installations, while enhancing other aspects like angular and energy resolution. These goals require the use of at least three different sizes of telescopes. CTA will comprise two arrays (one in the Northern hemisphere and one in the Southern hemisphere) for full sky coverage and will be operated as an open observatory. A prototype for the Medium Size Telescope (MST) type is under development and will be deployed in Berlin by the end of 2011. The MST prototype will consist of the mechanical structure, drive system and active mirror control. Four CCD cameras and a weather station will allow the measurement of the performance of the instrument. The ALMA Common Software (ACS) distributed control framework has been chosen for the implementation of the control system of the prototype. In the present approach, the interface to some of the hardware devices is achieved by using the OPC Unified Architecture (OPC UA). A code-generation framework (ACSCG) has been designed for ACS modeling. In this contribution the progress in the design and implementation of the control system for the CTA MST prototype is described. (authors)

[en] CTA (Cherenkov Telescope Array) is one of the largest ground-based astronomy projects being pursued and will be the largest facility for ground-based γ-ray observations ever built. CTA will consist of two arrays (one in the Northern hemisphere and one in the Southern hemisphere) composed of telescopes of several sizes. A prototype for the Medium Size Telescope (MST) of a diameter of 12 m will be installed in Berlin by the end of 2012. This MST prototype will be composed of the mechanical structure, drive system and mirror facets mounted with powered actuators to enable active control. Five Charge-Coupled Device (CCD) cameras and a weather station will allow the measurement of the performance of the instrument. The Atacama Large Millimeter/submillimeter Array (ALMA) Common Software (ACS) distributed control framework is currently being considered by the CTA consortium to serve as the array control middleware. In order to evaluate the ACS software, it has been decided to implement an ACS-based readout and control system for the MST prototype. The design of the control software is following the concepts and tools under evaluation within the CTA consortium, like the use of a Unified Modeling Language (UML) based code generation framework for ACS component modeling, and the use of OPen Connectivity-Unified Architecture (OPC UA) for hardware access. In this contribution, the progress in the implementation of the control system for this CTA prototype telescope is described.

[en] The H1 detector at HERA at DESY presently undergoes a major upgrade. In this context silicon strip detectors have been installed at the beginning of 1995. The high bunch crossing frequency of HERA (10.4 MHz) demands a novel readout architecture which includes pipelining, signal processing and data reduction at a very early stage. The front end readout is hierarchically organized. The detector elements are read out by the APC chip which contains an analog pipeline and performs first background subtraction. Up to five readout chips are controlled by a Decoder Chip. The readout processor module (OnSiRoC) operates the detectors, controls the Decoder Chips and performs a first level data reduction. The paper describes the readout architecture of the H1 silicon detectors and performance data of the complete readout chain. (orig.)

[en] The H1 detector at HERA at DESY undergoes presently a major upgrade. In this context silicon strip detectors have been installed at beginning of 1995. The high bunch crossing frequency of HERA (10.4 MHz) demands a novel readout architecture which includes pipelining, signal processing and data reduction at a very early stage. The front end readout is hierarchically organized. The detector elements are read out by the APC chip which contains an analog pipeline and performs first background subtraction. Up to five readout chips are controlled by a Decoder Chip. The readout processor module (OnSiRoC) operates the detectors, controls the Decoder Chips and performs a first level data reduction. The paper describes the readout architecture of the H1 Silicon Detectors and performance data of the complete readout chain. (orig.)