[en] Programmable Logic Device (PLD), especially Complex PLD (CPLD) or Field Programmable Logic Array (FPGA), has been growing in interest in nuclear Instrumentation and Control (I and C) applications. PLD has been applied to replace an obsolete analog device or old-fashioned microprocessor, or to develop digital controller, subsystem or overall system on hardware aspects. This is the main reason why the PLD-based I and C design provides higher flexibility than the analog-based one, and the PLD-based I and C systems shows better real-time performance than the processor-based I and C systems. Due to the development of the PLD-based I and C systems, their nuclear qualification has been issued in the nuclear industry. Verification and Validation (V and V) is one of necessary qualification activities when a Hardware Description Language (HDL) is used to implement functions of the PLD-based I and C systems. The life cycle V and V process, described in this paper, has been defined as satisfying the nuclear V and V requirements, and it has been applied to verify Correctness, Completeness, and Consistency (3C) among design outputs in a safety-grade programmable logic controller and a safety-critical data communication system. Especially, software engineering techniques such as the Fagan Inspection, formal verification, simulated verification and automated testing have been defined for the life cycle V and V tasks of behavioral, structural, and physical design in VHDL