How do you perform timing analysis for multi-voltage and multi-mode designs?

1 Timing analysis challenges

One of the challenges of STA is to handle multi-voltage and multi-mode designs, which are commonly used to reduce power consumption and increase functionality. Multi-voltage designs use different supply voltages for different parts of the circuit, while multi-mode designs use different configurations or modes of operation for different scenarios. These techniques introduce additional complexity and variability to the timing analysis, as the delay values depend on the voltage level and mode of the circuit. Moreover, there may be interactions or dependencies between different voltage domains or modes, such as level shifters, isolation cells, or mode control signals.

2 Timing graph and arcs optimization

In order to perform STA for multi-voltage and multi-mode designs, the timing graph and arcs must be optimized to accurately reflect the delay values and constraints. This can be achieved by utilizing various techniques such as voltage-aware timing analysis. This involves assigning different delay values to the timing arcs based on the voltage level of the source and destination nodes. For instance, if a node has a high voltage level its output delay will be lower than if it has a low voltage level. Moreover, if an arc connects two nodes with different voltage levels its delay will be higher than if they have the same voltage level. Additionally, mode-aware timing analysis requires assigning different delay values and constraints to the timing arcs depending on the mode of operation of the circuit. Furthermore, scenario-based timing analysis involves creating and analyzing multiple scenarios that represent different combinations of voltage levels and modes of the circuit. This allows for identifying worst-case and best-case scenarios, as well as the trade-offs and conflicts between different scenarios.

3 Timing analysis tools and methods

To perform timing analysis for multi-voltage and multi-mode designs, there are various tools and methods available. Static timing analysis tools, such as PrimeTime, Tempus, ETS, and Nanotime, can automatically create and optimize the timing graph and arcs based on the circuit netlist, library files, and design constraints. They can also perform voltage-aware, mode-aware, and scenario-based timing analysis. Additionally, user-defined scripts and commands like Tcl, SDC, TCC, and POCV can be used to customize the static timing analysis process. Moreover, timing models and libraries like Liberty, CCS, ECSM, and NLDM provide data files containing the physical characteristics of the circuit's logic elements and interconnects. These can be used to account for operating conditions like supply voltage, temperature, and process variation.

4 Timing analysis best practices

To perform timing analysis for multi-voltage and multi-mode designs effectively and efficiently, there are some best practices to follow. Define clear and consistent voltage levels, modes, scenarios, and constraints for the circuit with meaningful names and labels. Also, use standard and compatible formats and tools for the timing models, libraries, netlists, scripts, and commands. Validate and verify the timing graph and arcs for multi-voltage and multi-mode designs to ensure accuracy. Additionally, optimize and improve the timing performance and power consumption of the circuit by resolving timing violations, slack issues, critical paths, or power hotspots. Techniques such as sizing, buffering, clustering, gating, or voltage scaling can be used to enhance the timing and power characteristics of the circuit.