Blue Pearl Software

With High Reliability applications, little coding mistakes can add up to big problems. With the Visual Verification Suite, designers avoid costly and time-consuming design spins due to simulation versus hardware mismatches, invalid timing constraints as well as clocking and reset issues that can cause metastability problems. We would be happy to show you how it works: https://lnkd.in/gXnwpjbs #fpgadesign #embeddedsystems #CDC #clockdomaincrossing #digitlalogic #rtldesign #verilog #VHDL

If you write RTL for FPGAs and are not checking for Clock Domain Crossing (CDC) issues, this is your opportunity to improve code quality while increasing productivity. The Visual Verification Suite now includes non-transitive clock groups in alignment with Accellera Systems Initiative on a CDC standard.   What are non-transitive clock groups, and how does this new support benefit you? Read our blog to find out: https://lnkd.in/g_dnf5vG   #fpgadesign #embeddedsystems #CDC #clockdomaincrossing #digitlalogic #rtldesign #verilog #VHDL

If you write RTL for FPGAs and are not using advanced static verification, this is your opportunity to improve code quality while improving productivity, we would be happy to show you how. Get started at https://lnkd.in/gXnwpjbs   #fpgadesign #embeddedsystems #CDC #clockdomaincrossing #digitlalogic #rtldesign #verilog #VHDL

From all of us here at Blue Pearl Software, have a fun and safe Halloween! https://lnkd.in/gXnwpjbs

Part 4: You can’t manage what you don’t measure This is the final episode of our four-part video series, ‘Designing High Reliability FPGAs leveraging Blue Pearl Software’s Visual Verification Suite.’ In this short video, Adam Taylor CEng FIET, founder of Adiuvo Engineering & Training Ltd, explains how Adiuvo uses the Visual Verification Suite’s Management Dashboard to monitor their #FPGA #verification progress as well as for project sign off. For more information, please visit our website https://lnkd.in/gXnwpjbs  #fpgadesign  #embeddedsystems  #CDC  #clockdomaincrossing  #electronics  #digitlalogic  #engineering  #rtldesign  #verilog

Part 3: Avoiding Metastability In this third short video, Adam Taylor CEng FIET, founder of Adiuvo Engineering & Training Ltd, explains how they avoid FPGA metastability by leveraging the clock and reset domain crossing analysis within the Visual Verification Suite. To learn more, please visit https://lnkd.in/gXnwpjbs #fpga #fpgadesign #CDC #clockdomaincrossing #electronics #digitlalogic #engineering #verification #rtldesign #verilog #VHDL

Designing High Reliability FPGAs? In part 2 of this video series we again hear from Adam Taylor, founder of Adiuvo Engineering & Training Ltd, and learn how his team "verifies as they code" when designing high reliability FPGAs. To learn more visit: https://lnkd.in/gXnwpjbs #fpga #fpgadesign #embeddedsystems #CDC #electronics #digitlalogic #engineering #verification #rtldesign #verilog #VHDL

Designing High Reliability FPGAs? In this short video we hear from Adam Taylor CEng FIET, founder of Adiuvo Engineering & Training Ltd, to gain his insight on the challenges of designing high reliability FPGAs and how the Visual Verification Suite gives Adiuvo an edge on their competition. To learn more https://lnkd.in/gXnwpjbs #fpga #fpgadesign #embeddedsystems #CDC #clockdomaincrossing #electronics #digitlalogic #engineering #verification #rtldesign #verilog

If you are attending the FPGAworld conference in Stockholm next week, please stop by the Blue Pearl Software booth. You will see firsthand how adding static verification along with clock and reset domain crossing analysis accelerates your FPGA development. Can't make it? Schedule a private demo here: https://lnkd.in/gXnwpjbs #FPGAWorld #fpga #fpgadesign #embeddedsystems #CDC #clockdomaincrossing #electronics #digitlalogic #engineering #verification #rtldesign #verilog

We totally agree with you Adam Taylor, “Like many things in engineering, it is better to think about pipelining of data paths from day one. The work involved in addressing the issue later, when trying to achieve timing closure, might be considerable and costly.” The Visual Verification Suite, with its Long Path Analysis, allows you to find and fix long combinational paths before simulation and synthesis to help avoid late and costly design changes. Give it a try. Learn more here https://lnkd.in/gXnwpjbs