Axiomise’s Post

In about 2 minutes, you'll get an idea of why formal? what we have done with it? and the scale of designs we have verified with formalISA. From bugs, to proofs, and intelligent debug and coverage we have spent 5 years testing this product in field. We can debate all we like, but it may be better to just do it! #formalverification #riscv #socformal

Synchronous FIFO. Full environment. Assertions verified. Complete coverage.It is on github now. https://lnkd.in/d3qaBaxp #DigitalVerification #UVM #SystemVerilog

#HSRV #Phase1 #Post7 : Building a RISC-V Processor  Hello, LinkedIn community! 🔍 Previous Post Recap: https://lnkd.in/gVJxbKCH In the last update, we talked about the creation of the top-level SoC Testbench. Now our SoC has been tested with the official RISC-V International's test suite for the RV32I User Interface ✅ Test Results Passed: 38/40 Test Cases Failed: 2 Test Cases (fence_i.s and jalr.s) 🛠️ Understanding the Failures 1. fence_i.s Test Case Possible Issue: Instruction Fetch The fence.i instruction is designed to ensure that all previous stores are globally visible before subsequent instructions are fetched. A failure in this test could indicate that the instruction fetch buffer is not being correctly flushed, leading to stale instructions being executed. 2. jalr.s Test Case Possible Issues:    A) Incorrect PC Calculation: The jalr instruction computes the target address by adding an offset to the base register and zeroing the least significant bit. If this calculation is incorrect, the test will fail.    B) Incorrect Register Write-Back: The jalr instruction should write the address of the next instruction to the link register (rd). Failure here could mean the address isn't correctly calculated or stored.    C) Exception Handling: If the jalr instruction causes an exception, it may indicate a need for improved exception handling logic. 🔍 Next Steps: Debugging Process Design Review: We'll carefully review the design and implementation of the fence.i and jalr instructions to identify any potential flaws or missing components. Checking the Test Bench: The test bench will be re-evaluated to ensure that it correctly simulates all scenarios and that there are no issues in the way tests are executed or results are interpreted. This step will be crucial in refining the SoC to meet the stringent requirements of the RISC-V ISA. 📂 Track Progress Follow the detailed progress on my GitHub repository: https://lnkd.in/g33axenX 💬 Engage with Me I’m always open to suggestions, feedback, and discussions. Feel free to drop a comment or message with any insights or questions you may have. Thank you for following along, and stay tuned for more updates! #HardwareSecurity #VLSI #RISCVDebugging #TechJourney #RISCV #LearningFromScratch #StayTuned

Eliminate system inefficiency with our software and tools. Advanced tracing techniques offer unparalleled visibility into the complex dynamics of modern microarchitectures, with fine-grained controls to zero in on performance-critical areas of the system to achieve peak performance. From simple run control debug and cross-triggering to advanced multicore trace solutions, all are pre-integrated and verified together with MIPS RISC-V IP Cores in a single deliverable. #software #RISCV https://lnkd.in/g_Zs3cT6

Vulnerability Details : CVE-2024-0132 NVIDIA Container Toolkit 1.16.1 or earlier contains a Time-of-check Time-of-Use (TOCTOU) vulnerability when used with default configuration where a specifically crafted container image may gain access to the host file system. This does not impact use cases where CDI is used. A successful exploit of this vulnerability may lead to code execution, denial of service, escalation of privileges, information disclosure, and data tampering. CVSS 9.0 Referecia: https://lnkd.in/eFk39EtA

[Armv8-A] Exception-generating instruction - HVC debugging via TRACE32 Hello, friend, One of the most challenging aspects of learning about #Armv8-A architecture is understanding #exception handling. Without experiencing debugging related to exception handling, it is hard to find out what happens after an exception occurs. If you watch this video, you will see the following when running the HVC instruction using #TRACE32:  - How the program counter branches to the exception vector address.  - How the exception level switches from #EL1 to #EL2.  - How the #guest_OS works in the hypervisor environment. Please note that this video is included in the following lecture. Title: Armv8 Architecture: Exception Level and Exception state Link:  https://lnkd.in/gPybaSaq If you want to explore how exception levels switch, you can refer to it. I hope this material is useful to you. If you find it helpful, please follow me Austin Kim. BR, Austin Kim

#Day55 of #RTLCodingChallenge (TB to verify Parameterized classes in SV) ➡ Parameterized classes are useful when the same class needs to be instantiated differently. ➡ The default parameter can be set in the class definition. These parameters can be overridden when it is instantiated. ➡ The parameter can be constant values and data types. 📌 GitHub Repository Link: https://lnkd.in/g8GQGCsW #verilog #SV #DesignAndVerification #VLSI

It's 2024, and #riscv RISC-V is rapidly gaining momentum. It has become even more relevant as a global geo-politics is making it difficult to source the latest chip designs from other countries. Also, there are now methods to create relatively low-cost low volume production runs of custom advanced chips including RISC-V. In this video I run through a way to get an RISC-V emulator up and running so that you can get started. https://lnkd.in/eK2ZRhNv https://lnkd.in/eGRXcsPG

Hi! I'd like to share my work on the RISC-V (RV32I) architecture. I learned about and developed the RISC-V (RV32I) single cycle processor, which is capable of carrying out all of the fundamental instructions listed in the RISC-V ISA Manual. It has five stages as Fetch , Decode , Execute , Memory and Write back. I got some Fundamentals Insight of Computer Architecture and RISC ISA: - Fundamental concepts of computer architecture and processor design - Hands-on exposure to the unprivileged RISC-V Instruction Set Architecture (ISA) - Building a single-cycle RV32I compliant processor from scratch on Logic Simulator Called Logisim software. I Would like to Thanks Abdul Muheet Ghani for helping me out on this and Under the guidance of Him, this RV32I single cycle processor was developed. Below is the Attach Simulation of my Single Cycle CPU, the RV32I.

OpenVINO compiler backend with ARM Just In Time compilation (https://lnkd.in/e39nees2) in practice: #OpenVINO, #Intel