Erling Hedkvist’s Post

This week’s online workshop - Designing with the Versal Adaptive SoC: Memory Interfaces 📅December 19-20 ⏰Available worldwide In partnership with Core-Vision B.V. and Technically Speaking, Doulos is delighted to invite you to attend this AMD sponsored workshop (worth $990) for FREE! Presented in 2 half-day sessions by an AMD Authorized Training Instructor, with live Q&A, this workshop provides a system-level understanding of AMD Versal™ adaptive SoC memory interfaces. Workshop overview: ✅ You will learn about: Memory controller architecture, IP generation, simulation, and implementation are covered as well as additional info on PCB design issues. ✅ Topics include: DDRMC building blocks, ports and attributes, design through to implementation using the hardened memory controller, DDR4 & LPDDR4 debugging, performance tuning and board design requirements. ✅ It is live and interactive: The workshop is designed to maximize individual engagement and learning. You are encouraged to informally ask pertinent questions throughout, to actively participate in the learning process. ✅ Attending is easy! The workshop has been created to be accessible by a wide audience with standard technology requirements. Find out more & register👉 https://lnkd.in/eujKWBxB #workshop #doulostraining #amd #freeworkshop #versal

Great News! We have added the ability to connect two #AMD #Radeon #RX6400 4GB #graphics cards to the #CPU system, powered by two #Intel Xeon Silver 4108 processors. This upgrade expands the capabilities and performance potential of the #Dell PowerEdge T640 platform. More about it, find in our next article: https://lnkd.in/d8hetdsT

AXI4-Lite is a simplified, low-complexity subset of the AXI4 (Advanced eXtensible Interface 4) protocol, designed by ARM for memory-mapped communication within SoC (System-on-Chip) environments. It is optimized for applications that don’t require high-bandwidth data transfers or advanced features, like burst transfers, making it ideal for simple peripherals and control register access. --> Overview of AXI4-Lite #AMBA #AXI #SoC_Design #Design_Verification #System_Verilog #UVM

Renice four channel 250Msps 16bit AD FMC sub-card This board is based on the FMC standard board, which realizes the function of four channel 16-bit/250Msps ADC. Following VITA 57 standard, the board card can be directly connected to xilinx company or our company's FPGA board. The ADC device USES ADI 9467 chip, and users can configure the working state of the chip through the FMC interface.

Last week, we announced our record-breaking STAC benchmark for tick-to-trade latency of 13.989 nanoseconds with nxFramework. Our existing clients benefit from the latency boost gained in this update, find out more about our commitment to FPGA development > https://bit.ly/4cu2IH9 Olivier Cousin Exegy's director of FPGA solutions is quoted below, learn more about his team's achievements by reading the full press release linked above. #HFT #ULL #FPGAdevelopment #tradingtechnology

Introducing the *SAF1* from Annapolis Micro Systems - a SFF module that integrates the Altera Agilex 9 Direct RF-Series FPGA and four channels each of 64 GSps A/D and D/A converting at 10-bit resolution. https://lnkd.in/e2BARmQF

#LowLatency #Trading: AMD just set a new tick-to-trade #STAC-T0 record in collaboration with Exegy: 13.9 ns! Previous record (also held by AMD) was 24.2 ns. The new AMD and Exegy STAC-T0 high-precision timestamping benchmark record was achieved with the AMD Alveo™ UL3524 accelerator card, a purpose-built FinTech card for fast trade execution, powered by an AMD Virtex™ UltraScale+™ FPGA, running on the Exegy nxFramework and Exegy nxTCP-UDP-10g-ULL IP Core in a Dell PowerEdge R7525 server with AMD EPYC™ 7313 processors, with an Arista 7130 platform and an Arista MetaWatch 7130 device. If you have a STAC login, the report is available here: https://lnkd.in/eVqtkxSw #HFT #FSI

What’s the secret to faster design cycles and better system performance? It’s all about FPGA and software co-design! 💡 At our Fidus Tech Talk on October 22, we’re revealing the key strategies to boost real-time performance in MPSoC architectures. With platforms like AMD Zynq Ultrascale+ and Intel Stratix 10, you’ll see how to unlock game-changing efficiencies. Don’t just design—innovate. 🔧 📅 When? Tuesday, October 22, 11 AM ET 🔗 Sign up now: https://hubs.la/Q02TD_M30 #EmbeddedSystem #FPGA #EmbeddedSoftware #MPSoCIntegration

Check out the latest edition of the Microchip FPGA & SoC TechBytes!

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