Gunnar Pope, Ph.D.’s Post

🎉 I am glad to announce the publication of my latest article on LinkedIn! 🎉 This paper is the extended version of our previous conference paper, "Low-Cost Hardware Security of Laplace Edge Detection and Embossment Filter Using HLS Based Encryption and PSO", published in "9th IEEE International Symposium on Smart Electronic Systems (IEEE – iSES), 2023" and received the Springer Nature Best Paper Award. The increasing usage of image processing applications in modern technological environments is driven by their ability to enhance visual quality in diverse applications, from social media to medical imaging. The design of these cores as dedicated application-specific hardware intellectual property (IP) must ensure optimized performance and security. It is crucial to optimize these designs while enhancing their security to create a robust, secure design flow that can provide security against hardware security threats like IP piracy and fraudulent ownership claim. The proposed methodology introduces a low-cost security framework for application-specific hardware systems using an HLS-aided fusion watermarking framework and particle swarm optimization-driven design space exploration (PSO-DSE) process. The proposed approach demonstrates the generation of a multi-stage encryption-based signature along with the IP seller’s fingerprint biometric-based signature, which is further fused to generate the final watermark signature. It allows the embedding of a greater number of secret watermark constraints offering lower probability of coincidence and higher tamper tolerance without incurring design overhead, compared to prior works. 🌐💡#hardwaresecurity #biometric #reliability #imagefilters #hardwareaccelerator #intellectualpropertyrights #digitaltransformation #innovation #cybersecurity #vlsi #CAD. Publication link: https://lnkd.in/g8fJsv3A

I’m thrilled to share that my teammate, Rajat Siddangouda Patil, and I just completed a comprehensive presentation on “Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques” as part of our coursework for ECE 568: Advanced Micro Architecture at the University of Illinois Chicago. Our research focused on RowHammer, a critical vulnerability in modern DRAM (Dynamic Random Access Memory) that occurs due to repeated accesses to a single row, which can lead to bit flips in neighboring rows. These bit flips are more than just memory corruption—they can cause significant security breaches, system instability, and data loss, especially as DRAM chips become denser and more compact. 🔍 Key Insights from Our Analysis: As newer DRAM technologies, particularly LPDDR4 and DDR4, become more densely packed, we observed that they are increasingly vulnerable to RowHammer attacks. In fact, some of the latest LPDDR4 chips experience bit flips with as few as 9.6k activations compared to older generations like DDR3, which required 69.2k activations. The study also tested five state-of-the-art mitigation techniques, but the results indicated that many of these defenses may not scale effectively to protect future DRAM technologies. For instance, approaches like Target Row Refresh (TRR) and increasing refresh rates help reduce vulnerability but come with significant performance overhead. The problem of RowHammer is not just theoretical. Our findings demonstrated how easily this vulnerability can be exploited, and it remains an area of concern for both hardware and security researchers. 💡 Looking Forward: Our presentation emphasized the need for innovative and scalable solutions. As DRAM technology continues to evolve, current mitigation techniques may become obsolete. Future solutions need to balance performance with security to ensure the integrity of computing systems. We are proud to contribute to this important area of research and hope it sparks conversations about hardware security and the future of memory technologies. Big thanks to our course instructor and everyone who supported us during this deep dive into the world of micro-architecture and memory security. 🙌 If you’re interested in discussing more about DRAM vulnerabilities or want to dive deeper into RowHammer research, feel free to connect! #RowHammer #DRAM #MemorySecurity #VulnerabilityResearch #Cybersecurity #MicroArchitecture #ECE568 #Research #UniversityOfIllinoisChicago #TechInnovation #DataIntegrity

It was a pleasure collaborating with Ambarish Pathak on our presentation, “Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques,” for ECE 568 at UIC. We explored the vulnerabilities of modern DRAM technologies to RowHammer attacks and highlighted the challenges of balancing performance with security. Excited to share our findings and keep the conversation going around memory security and micro-architecture! #RowHammer #DRAM #ECE568 #Research #TechInnovation #UIC #HighPerformace #Computing.

https://lnkd.in/gNvYUVnm Well, apparently speculative execution causing issues is not patented by Intel... Researchers have figured a way to leverage this feature to break ARM's memory protection feature (memory tag extension).

"[T]he most expensive components of the RayV Lite are the lens used for focusing its relatively cheap laser [pointer] & an #FPGA chip that serves as its timing mechanism, each of which costs close to $100, as well as the $68 #RaspberryPi minicomputer that allows it to be controlled & programmed" https://lnkd.in/g_XME622

🚗🔐 Post-quantum Firmware Over-the-Air optimizations with Falcon and SHAKE 🔐🚗   We're thrilled to share further findings from a study focusing on Firmware Over-The-Air (FOTA) systems, which are crucial for modern automotive software updates. This research evaluated two quantum-resistant digital signature algorithms, Falcon and Dilithium, within automotive FOTA systems. Results highlight Falcon's efficiency in signature verifications — a key performance factor as vehicles primarily verify rather than generate digital signatures.   Interestingly, the research underscores that the hashing of large firmware updates, not the digital signature algorithm, is the primary performance bottleneck. Addressing this, a hardware accelerator for the SHAKE hash function was developed, significantly boosting FOTA execution times by two orders of magnitude. These enhancements align with UNECE Regulation 155 and 156 to manage the cybersecurity and the software updates for automotive cybersecurity as post-quantum cryptography needs to be a consideration today.   Stay up-to-date with everything automotive cybersecurity and reach out to us at vultara.com/contact!   Source: https://lnkd.in/gf6S3xNq Reaserchers: Gianluca Dini Sergio Saponara Stefano Di Matteo Pericle Perazzo #AutomotiveInnovation #Cybersecurity #QuantumComputing #FutureMobility #Vultara

If you are interested in the development of intrusion detection systems (IDS) at the edge level, we tackle this issue, in our recent publication accepted to ARC24, by analyzing the several intelligent IDS (I-IDS) with a spical focus on requirements of reconfigurable Edge devices. Then, we implemented our proposed IDS on state-of-the-art FPGA technology as (1) a purely dataflow processor and compared it to (2) a co-designed approach using RISC-V soft-core processor on FPGA. Paper title: Reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach. Authors: Wadid Foudhaili , Anouar Nechi, Celine Thermann, Mohammad Al Johmani, Rainer Buchty, Mladen Berekovic & Saleh Mulhem https://lnkd.in/dfffXBSk The paper will be presented next week in the 20th International Symposium on Applied Reconfigurable Computing - ARC 2024, Aveiro - Portugal. #ids #fpga #riscv #edge #security

Excited to share that our paper, "𝗔𝘂𝘁𝗼𝗣𝗮𝘁𝗰𝗵: 𝗔𝘂𝘁𝗼𝗺𝗮𝘁𝗲𝗱 𝗚𝗲𝗻𝗲𝗿𝗮𝘁𝗶𝗼𝗻 𝗼𝗳 𝗛𝗼𝘁𝗽𝗮𝘁𝗰𝗵𝗲𝘀 𝗳𝗼𝗿 𝗥𝗲𝗮𝗹-𝗧𝗶𝗺𝗲 𝗘𝗺𝗯𝗲𝗱𝗱𝗲𝗱 𝗗𝗲𝘃𝗶𝗰𝗲𝘀", has been accepted at ACM CCS 2024! 🎉 As embedded devices become increasingly integrated into our daily lives—from implantable medical devices to power grids and consumer products—their security becomes critical. Cyberattacks on these devices can lead to serious, even life-threatening consequences, making timely patching essential for mitigating such risks. In this paper, we propose 𝗔𝘂𝘁𝗼𝗣𝗮𝘁𝗰𝗵, a novel hotpatching technique that 𝙖𝙪𝙩𝙤𝙢𝙖𝙩𝙞𝙘𝙖𝙡𝙡𝙮 generates patches to fix security vulnerabilities. By statically analyzing official patches using the LLVM compiler, AutoPatch enables mission-critical embedded devices to be patched without the need for a reboot. Our evaluation across various embedded boards and hardware demonstrates that this technique is platform- and architecture-independent. 📄 𝘗𝘢𝘱𝘦𝘳: AutoPatch: Automated Generation of Hotpatches for Real-Time Embedded Devices 👥 𝘈𝘶𝘵𝘩𝘰𝘳𝘴: Mohsen Salehi, Karthik Pattabiraman 🔗 𝘓𝘪𝘯𝘬 𝘵𝘰 𝘱𝘢𝘱𝘦𝘳: https://lnkd.in/gQEFC_YQ 🔗 𝘈𝘳𝘵𝘪𝘧𝘢𝘤𝘵𝘴: https://lnkd.in/gd2PxVBE Unfortunately, I won’t be able to attend the conference, but Karthik Pattabiraman will be presenting our work on 𝗪𝗲𝗱𝗻𝗲𝘀𝗱𝗮𝘆, 𝗢𝗰𝘁𝗼𝗯𝗲𝗿 𝟭𝟲𝘁𝗵, 𝟮𝟬𝟮𝟰, in 𝗦𝗮𝗹𝘁 𝗟𝗮𝗸𝗲 𝗖𝗶𝘁𝘆, 𝗨𝗧, USA, during Session 𝟱-𝟰. Feel free to reach out if you'd like to learn more or have any questions! 🙌 #CyberSecurity #EmbeddedDevices #LLVM #Compiler #StaticAnalysis #ACM

Just Published Review Article in our journal (Mesopotamian journal of Cybersecurity) indexed in Scopus, CiteScore(4.4). Title: Memristive-Based Physical Unclonable Function Design of Authentication Architectures: A Systematic Review. DOI: https://lnkd.in/gK-pjMdM Keywords: Hardware Security, Physically Unclonable Function (PUF), Memristor (M), Ring Oscillator PUF (RO-PUF), Field Programmable Gate Arrays (FPGA). Highlights: This study examines the use of Physically Unclonable Functions (PUFs) as unique digital fingerprints for enhancing hardware security, particularly through FPGA-based implementations. It focuses on improving PUF circuits by integrating memristors into ring oscillators, aiming to boost key performance metrics like uniqueness, uniformity, and reliability. The study compares various approaches and finds that memristor-enhanced PUFs significantly improve security, showing metrics of 48.57% uniqueness, 51.43% uniformity, and 51.43% bit-aliasing. These results confirm the effectiveness of memristor-based PUFs in enhancing security through robust encryption and verification methods.

#Cryptography paper Detour-RS: Reroute Attack Vulnerability Assessment with Awareness of the Layout and Resource by Minyan Gao, Liton Kumar Biswas, Navid Asadi and Domenic Forte Department of Electrical and Computer Engineering, University of Florida open access, read full paper: https://lnkd.in/gZQyqxV7 #hardware #security; #microprobing #attacks; #reroute attacks; #integrated #circuits; #focused #ion #beam Abstract: Recent decades have witnessed a remarkable pace of innovation and performance improvements in integrated circuits (ICs), which have become indispensable in an array of critical applications ranging from military infrastructure to personal healthcare. Meanwhile, recent developments have brought physical security to the forefront of concern, particularly considering the valuable assets handled and stored within ICs. Among the various invasive attack vectors, micro-probing attacks have risen as a particularly menacing threat. These attacks leverage advanced focused ion beam (FIB) systems to enable post-silicon secret eavesdropping and circuit modifications with minimal traceability. As an evolved variant of micro-probing attacks, reroute attacks possess the ability to actively disable built-in shielding measures, granting access to the security-sensitive signals concealed beneath. To address and counter these emerging challenges, we introduce a layout-level framework known as Detour-RS. This framework is designed to automatically assess potential vulnerabilities, offering a systematic approach to identifying and mitigating exploitable weaknesses. Specifically, we employed a combination of linear and nonlinear programming-based approaches to identify the layout-aware attack costs in reroute attempts given specific target assets. The experimental results indicate that shielded designs outperform non-shielded structures against reroute attacks. Furthermore, among the two-layer shield configurations, the orthogonal layout exhibits better performance compared to the parallel arrangement. Furthermore, we explore both independent and dependent scenarios, where the latter accounts for potential interference among circuit edit locations. Notably, our results demonstrate a substantial near 50% increase in attack cost when employing the more realistic dependent estimation approach. In addition, we also propose time and gas consumption metrics to evaluate the resource consumption of the attackers, which provides a perspective for evaluating reroute attack efforts. We have collected the results for different categories of target assets and also the average resource consumption for each via, required during FIB reroute attack.