Ichiro T.’s Post

"Why is Hard IP a Better Solution for #Embedded FPGA (#eFPGA) Technology?" by Brian Faith, QuickLogic Corporation https://lnkd.in/ecJ-UCqy Once someone has decided to move forward with an embedded FPGA design, they have a few decisions to make. One of the most important is whether to choose soft IP or hard IP.

an interesting read if you want to understand the nuances between using eFPGA Hard I/P vs eFPGA soft I/P, not always obvious just how much work goes on in the background to guarantee timing across an FPGA array and input back into the tool chain. https://lnkd.in/eGUtWGsU

🚀 New Blog Post Alert! 🚀 Excited to share our latest article on Getting Started with CI for AMD (Xilinx) FPGA Synthesis! Learn how to streamline FPGA design using BeetleboxCI, from creating a hardware testbench to automating synthesis and testing with continuous integration. 🔧 Key Takeaways: Automate FPGA synthesis and testing Harness the power of Vivado and ILA Boost efficiency with CI practices 👉 Read the full article to transform your FPGA development process: https://lnkd.in/eUBTuXU5 #FPGA #AMD #ContinuousIntegration #BeetleboxCI #HardwareDesign #Innovation #DigitalDesign

⚠️ Attention all you FPGA designers and rogue hackers! Are you struggling with Timing Closure in your designs? Don't worry, you're not alone, I ran into issues tonight. But the good news is that there are solutions to this problem. By implementing the right practices and techniques, you can turn hard problems into exciting and easy ones. Here are three tips to get you started: 1. Start with Synthesis! Find the root of the problem to make a 10x impact on performance. Clues can be high levels of logic, high fanouts. If you can't meet timing (WNS/TNS) at synthesis, don't continue to implementation. The most significant return is mostly found at the RTL level. 2. Run the reports! (report_timing_summary, report_utilization, report_clock_interaction, report_methodology) Identify the top offenders. Always check the schematic for high WNS/TNS paths, cross-reference with device view, this will highlight from a physical dimension where the source & destination items exist (long travel lines = not good 🫣) 3. Use QoR Assessment/Suggestions! Vivado uses ML-based models that have worked for designs in the past, which can be cross-referenced with the current user design. A score range is given from a value of 1 (being the worst) to 5 (being the best). This is denoted as QoR assessment. QoR Suggestions is the secret sauce providing you dependable strategies to adopt or just information to be aware of such that you can review and assess the details in your design. Please checkout these poweful resources: - https://lnkd.in/gW-SQBh2 - https://lnkd.in/gG2bS5_W By implementing these practices, you'll be equipped with the tools to tackle Timing Closure like a pro. Keep pushing forward, and success will be within reach. #FPGA #TimingClosure #DesignTips #EngineeringTips

5 Reasons You Should Use Lattice Nexus or Avant For Your Next FPGA Project: 1. Best in class power - and it is not even close. Lattice Nexus and Avant are architected for low power and fabric performance. Other vendor's have mid-range products that waterfall from high-end families. Lattice's LUT4 architecture uses 75% less SRAM bits than LUT6, which means significantly less leakage. 2. Innovative and small package offerings. Our CertusPro-NX, with 100K LCs and 10G SerDes sits in a 9x9mm 256-ball ASG package. Our Avant-X with 637K SLCs and 25G SerDes can be had in a 15x15mm, 841-ball CSP. 3. Lowest total solution cost and footprint. No power sequencing or complex power distribution network is needed, even for our SerDes products. Gone are the days of a large power and passive component courtyard around your device. Did I mention our software tools are free to use for most of our products? 4. Dedicated support. If you are in the Southeast or Mid-Atlantic, you get to work with me and our great distribution partners directly. If not, I'll connect you to one of our experts in your region. No web forum or AI chat bot trying to answer your questions or support your design. 5. Simplified design tools. Our software tools reflect the design intention and use of our parts – small to mid-complexity programmable logic. Lattice Radiant is a ~2GB download and comes bundled with a plethora of design examples and access to our complete catalog of IP. FPGA designers relish the immediacy and intuitiveness of our modern tools... and you can quickly turn your design into a SoC with Lattice Propel. #lattice #FPGA #verilog #vhdl #avant

Large ASIC designs require multiple FPGAs for mapping but designing FPGA prototypes in-house is expensive and time-consuming. Learn how the Veloce proFPGA prototyping solution can accommodate a broad scope of verification requirements without compromising performance, usability and portability. https://sie.ag/3S9Sm5m

𝐃𝐞𝐦𝐲𝐬𝐭𝐢𝐟𝐲𝐢𝐧𝐠 𝐒𝐨𝐂 𝐕𝐞𝐫𝐢𝐟𝐢𝐜𝐚𝐭𝐢𝐨𝐧: 𝐀 𝐒𝐭𝐫𝐚𝐭𝐞𝐠𝐢𝐜 𝐀𝐩𝐩𝐫𝐨𝐚𝐜𝐡 𝐟𝐨𝐫 𝐅𝐥𝐚𝐰𝐥𝐞𝐬𝐬 𝐂𝐡𝐢𝐩 𝐃𝐞𝐬𝐢𝐠𝐧 In this recent article illuminates the nuanced steps of the SoC verification flow, a process that demands meticulous attention to detail and strategic planning. 🔍 𝐅𝐞𝐚𝐭𝐮𝐫𝐞 𝐄𝐱𝐭𝐫𝐚𝐜𝐭𝐢𝐨𝐧𝐬: The initial phase involves a deep dive into the SoC’s architecture, extracting its top-level functionalities. This stage is critical as any misinterpretation could lead to significant delays and design flaws. 📝 𝐒𝐨𝐂 𝐋𝐞𝐯𝐞𝐥 𝐕𝐞𝐫𝐢𝐟𝐢𝐜𝐚𝐭𝐢𝐨𝐧 𝐏𝐥𝐚𝐧: Defining the boundaries between SoC and IP verification is essential. It’s about identifying what needs verification at the SoC level versus the sub-block or IP level, ensuring clarity and focus. ♻️ 𝐑𝐞𝐮𝐬𝐚𝐛𝐢𝐥𝐢𝐭𝐲 𝐂𝐨𝐦𝐩𝐨𝐧𝐞𝐧𝐭𝐬: Efficiency is key. By identifying which components can be reused from block-level verification, we can significantly cut down on development time. 🔗 𝐕𝐞𝐫𝐢𝐟𝐲 𝐈𝐧𝐭𝐞𝐫𝐜𝐨𝐧𝐧𝐞𝐜𝐭𝐢𝐨𝐧𝐬: Ensuring that the communication between sub-blocks is flawless is paramount. This step verifies the integrity of the SoC’s internal communication pathways. 🔄 𝐏𝐥𝐚𝐜𝐞𝐡𝐨𝐥𝐝𝐞𝐫𝐬 𝐟𝐨𝐫 𝐔𝐩𝐝𝐚𝐭𝐞𝐬: Flexibility in the verification plan allows for the incorporation of new features as they emerge, ensuring the plan remains comprehensive and up-to-date. For those looking to delve deeper into the strategic intricacies of SoC verification, the full article provides a wealth of knowledge. https://lnkd.in/gNX5V3yQ #theartofverification #SoCVerification #ChipDesign #SystemOnChip #VerificationFlow #SemiconductorIndustry #IntegratedCircuits #ElectronicDesignAutomation #EDA #VLSI #ASICDesign #FPGA #HardwareVerification #DesignVerification #TechInnovation #EngineeringExcellence

#Embedded #FPGA CHANDLER, Ariz., February 15, 2024 — The embedded industry is seeing an increased demand for open-source RISC-V-based processor architectures, but there are still limited options when it comes to commercially available silicon or hardware. To fill this gap and help empower innovation, Microchip Technology (Nasdaq: MCHP) has launched the PolarFire® SoC Discovery Kit. By offering a user-friendly, feature-rich development … Read More → "Microchip’s Low-Cost PolarFire® SoC Discovery Kit Makes RISC-V and FPGA Design More Accessible for a Wider Range of Embedded Engineers" https://lnkd.in/gzugv65P

Question: If anyone can buy an FPGA, verify any design available to him and prototype it, then send the design to anywhere as well as produce a synthesis report, why isn't there more outsourcing in this field? Especially with the popularity of Hardware Accelerators and the increasing need for verification engineers?

Timing analysis is the cornerstone of successful FPGA design. While some design aspects may allow for flexibility, timing analysis is non-negotiable. Understanding and applying these principles is vital for ensuring digital circuits operate reliably and efficiently under all conditions. In this article, we will explore the essentials of Static Timing Analysis (STA), covering critical concepts like setup and hold times, maximum clock frequency, and Clock Domain Crossing (CDC). For more information refer to the article provided by Farhad Khodadady from our FPGA team: bit.ly/3XlgAgF #FPGA #statictiminganalysis #learninganddevelopment