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Hi Everyone #hiring #Silicon Validation & Test Engineers #Bangalore Role: #Silicon Validation & Test Engineers Experience : #3-7years Location : #Bangalore Job Summary : As a member of the customer engineering (CE) team for Comms-Enterprise-Datacenter (CED), you will play a critical role in supporting our sales and marketing team to drive design wins and revenue growth. You will serve as the timing advisor for our customers, helping them deliver the most robust system design with the highest performance.  You will also work closely with internal product team to ensure timely release of our innovative MEMS timing products that will transform the world of timing. Responsibilities: #Customer Support Collaborate with customers to solve their system requirements utilizing SiTime Products including timing architecture and clock trees pre/post-sales. Understand the customer system to fine tune the performance of our solution for the use case. Help customers to debug their system and component level timing issues during design. Process support tickets for the assigned customers and regions Be the #“customer voice” inside SiTime including product features, performance, schedule. #Products and roadmap Specify and create customer facing product collaterals and tools including datasheets, performance reports, #EVKs, software tools and demos. Perform competitive analysis vs. competing products. Contribute to roadmap definition by leveraging customer and application knowledge. Assist design team in debug of the silicon and supporting customer queries. Assist engineering team in device validation and characterization when needed, including developing bench validation and characterization plans, design and implement automation methods, and perform actual measurements.   Qualifications & Requirements (Education must be included):  Ability to work with #customers and #sales team to recommend solutions and debug design issues. Experience in test and measurements of timing devices (time and frequency domain) Hands on experience with #Python/C/C++ is a plus. Strong fundamentals and good knowledge of #circuit #analysis and design is a plus. Familiarity with Schematic capture and #PCB design skills  Expertise with common #lab equipment such as power supplies, High Bandwidth #Oscilloscopes, #Spectrum Analyzer, #Phase Noise Meters, #Frequency Counter etc.  Strong knowledge in #mixed #signal or #Analog #PCB design and debug. Specific experience with High-speed Timing chipsets and the design of their test and measurement solution is a plus.  Understanding of Transistor level circuit design is good to have for more involved chip debug and #Hardware Design.  A technology-related bachelor's degree or equivalent training with minimum 3 years of related experience. Interested Candidates Share your Updated CV-----> Poornima@perceptivessolutions.com  

🔔 High Priority Job Openings! 🔔 We have some high priority active requirements with one of our customers. If you or someone you know is interested, please share the resumes at ritesh@badgefree.com. Note: We need candidates who are available on short notice. Job Openings: SoC DV Lead (8+ yrs, Bangalore) Skills: #SoCVerification #CTestCases Description: Proficient in SoC verification and writing 'C' test cases for SoC DV. DFT Sr Engineer/Lead (5+ yrs, Bangalore) Skills: #DFTArchitectures #JTAG #ScanCompression #SynopsysTools Description: Understanding of DFT architectures like JTAG, Scan Compression Techniques, Synopsys tool experience. Physical Design (PD) (5-8 yrs, Bangalore) Skills: #Synthesis #PlaceAndRoute #CTS #TimingConvergence #IREMChecks #DRCLVSClosure #Innovus #FusionCompiler Description: Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks, and signoff DRC/LVS closure. Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM. Experience with Innovus tool is preferred, and a mix of Fusion Compiler & Innovus. IP DV (7+ yrs, Bangalore) Skills: #SV #UVM #IPVerification #DebuggingSkills Description: Proficient in SV/UVM based IP verification with good debugging skills. STA/Lead (8+ yrs, Bangalore) Skills: #TimingClosure #STA #ConstraintDevelopment #DFTConstraints Description: Well versed with timing closure (STA), timing closure methodologies, pre/post-layout constraint development to timing closure, handshake with the design team, and develop functional/DFT constraints. PCIE DV Lead (7+ yrs, Bangalore) Skills: #NetworkingProtocol Description: Experience on networking protocol. Analog Layout (6+ yrs, Bangalore/Hyderabad) Skills: #LowerNodes #FinfetTechnologies Description: Proficient in lower nodes and Finfet technologies. RTL Design Lead (8+ yrs, Bangalore) Skills: #PerlScripting #Lint #CDC #UPF #Constraints Description: Experience in Perl scripting, lint, CDC, UPF, constraints. Emulation (5+ yrs, Bangalore) Skills: #HAPS #Veloce #Palladium #Design #FPGA Description: Experience with HAPS, Veloce, Palladium, design, and FPGA. PDN (3-8 yrs, Bangalore) Skills: #EMIR #IRDrop #Redhawk Description: Experience with EMIR, IR Drop, Redhawk. Backend Power Optimization (3-8 yrs, Bangalore) Skills: #PTPX Description: Proficient in PTPX. PD CAD (3-5 yrs, Bangalore) Skills: #FusionCompiler Description: Experience with Fusion Compiler. FPGA (8-12 yrs, Hyderabad) Skills: #Coding #Validation #Verilog #C Description: Experience in coding, validation, Verilog, and C. Feel free to reach out for more details. Let's connect the right talent with the right opportunities! 🌟 #Hiring #JobOpenings #EngineeringJobs #BangaloreJobs #HyderabadJobs #ShortNoticeHiring #opentowork

Hello Connection, Greetings from TEKFORTUNE IT India Pvt. Ltd! We are #hiring for below #Full_time positions. (Position No: 1) Title: Analog Layout Engineer Experience: 4 10 years  Work Location: Bangalore (onsite) Notice Period: Immediate to 30 Days Max only. (Position No: 2) Title: Analog Mixed Signal Verification Experience: 6 10 years  Work Location: Bangalore (onsite) Notice Period: Immediate to 30 Days Max only. (Position No: 3) Title: Physical Design Engineer Experience: 5 14 years  Work Location: Bangalore (onsite) Notice Period: Immediate to 30 Days Max only. (Position No: 4) Title: Design Verification Engineer Experience: 5 15 years  Work Location: Bangalore (onsite) Notice Period: Immediate to 30 Days Max only. ****Note: Immediate to 30 Days Max only**** If interested, kindly share their CVs at the below mentioned email ID for a quick response. vinit.wankhede@tekfortune.com / +91-789-838-5987. #fulltime #full_Time #fulltimejobs #hiring #Jobs #JobChange #Job_Change #Opportunity #hiring #Permanent #TechJobs #Bangalore #WFO #Work_from_office #onsite #Engineer #Analog #Semiconductor #AnalogLayoutEngineer #SemiconductorJobs #AnalogDesign #EDA #Exploratory_Data_Analysis #EDAEngineer #HighSpeedSerDes #PowerManagement #Power_Management #Integrated_Circuit #Circuit #ICDesign #VLSIJobs #EngineeringCareers #AnalogMixedSignal #VerificationEngineer #AnalogDesign #CMOS #CMOSDesign #SpiceSimulations #CoSimulation #SystemVerilog #UVM #Universal_Verification_Methodology #VLSIVerification #Very_Large_Scale_Integration #VLSI #PhysicalDesignEngineer #FloorPlanning #PNR #Place_and_Route #STA #Static_timing_analysis #TilePVFixes #SignoffFlows #LeadEngineer #DesignVerification #Ethernet #SOC #System_on_chip #Programming #PERL #ShellScripting #Debugging #Shell_Scripting #USB #Universal_Serial_Bus #HBM #High_Bandwidth_Memory #DDR #Double_Data_Rate #PCIe #Peripheral_Component_Interconnect_Express #HSIOProtocols #CPlusPlus #C++ #TestBenchDevelopment

#hiring Senior Principal Engineer - Signoff, San Jose, United States, fulltime #jobs #jobseekers #careers #SanJosejobs #Californiajobs #Engineering Apply: https://lnkd.in/d_hs_Ddc Job Overview: Arm has formed a new group to develop outstanding silicon demonstrators based on Arm's IP compute sub-system solutions and addressing markets such as premium mobile, infrastructure and automotive. Using the latest nodes, e.g. 3nm today, and applying the latest SoC 2.5D and 3D technology, Arm's ambition is to demonstrate industry outstanding performance by architecting, designing, implementing, and fabricating innovative silicon chips. Responsibilities: Your responsibilities will involve developing challenging electrical signoff methodologies. These methodologies will balance accuracy and yield on silicon. The following are the immediate challenges we will be working on as a team: We will develop a Static Timing Analysis flow that is standardized and is usable by all silicon groups within Arm We will work on strengthening our methodologies to analyze static and dynamic IR drop on the SoC. We will release a qualified flow that enable STA with back annotated voltage Electromigration analysis at the SoC level is another key responsibility of this role. Including Local thermal effects as part of electromigration analysis is a key criteria! Soft Error rate is a key concern for Infrastructure and Automotive SoC's. We will develop methodologies to analyze and alleviate the impact of Soft Error rate on SoC's Required Skills and Experience : Experience in developing Signoff methodologies such as Aging, STA, EM IR in advanced process nodes. Experience in collaborating across silicon engineering groups in your organization as well as with EDA vendors Work experience in Physical Implementation and Signoff methodologies Must have worked on methodology development on 5nm or 3nm technologies Strong data analysis skills to fetch data, analyze and provide practical insights "Nice To Have" Skills and Experience : Masters in Electrical Engineering Strong coding skills in Python or R or an equivalent language Strong presentation skills Salary Range From $2 46,925.00 To $ 319,550.00 We value people as individuals and our commitment is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process. In Return: We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

#hiring Senior Principal Engineer - Signoff, San Jose, United States, fulltime #jobs #jobseekers #careers #SanJosejobs #Californiajobs #Engineering Apply: https://lnkd.in/eU9XYT9H Job Overview: Arm has formed a new group to develop outstanding silicon demonstrators based on Arm's IP compute sub-system solutions and addressing markets such as premium mobile, infrastructure and automotive. Using the latest nodes, e.g. 3nm today, and applying the latest SoC 2.5D and 3D technology, Arm's ambition is to demonstrate industry outstanding performance by architecting, designing, implementing, and fabricating innovative silicon chips. Responsibilities: Your responsibilities will involve developing challenging electrical signoff methodologies. These methodologies will balance accuracy and yield on silicon. The following are the immediate challenges we will be working on as a team: We will develop a Static Timing Analysis flow that is standardized and is usable by all silicon groups within Arm We will work on strengthening our methodologies to analyze static and dynamic IR drop on the SoC. We will release a qualified flow that enable STA with back annotated voltage Electromigration analysis at the SoC level is another key responsibility of this role. Including Local thermal effects as part of electromigration analysis is a key criteria! Soft Error rate is a key concern for Infrastructure and Automotive SoC's. We will develop methodologies to analyze and alleviate the impact of Soft Error rate on SoC's Required Skills and Experience : Experience in developing Signoff methodologies such as Aging, STA, EM IR in advanced process nodes. Experience in collaborating across silicon engineering groups in your organization as well as with EDA vendors Work experience in Physical Implementation and Signoff methodologies Must have worked on methodology development on 5nm or 3nm technologies Strong data analysis skills to fetch data, analyze and provide practical insights "Nice To Have" Skills and Experience : Masters in Electrical Engineering Strong coding skills in Python or R or an equivalent language Strong presentation skills Salary Range From $2 46,925.00 To $ 319,550.00 We value people as individuals and our commitment is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process. In Return: We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

🔔 High Priority Job Openings! 🔔 We have some high priority active requirements with one of our customers. If you or someone you know is interested, please share the resumes at ritesh@badgefree.com. Note: We need candidates who are available on short notice. Job Openings: SoC DV Lead (8+ yrs, Bangalore) Skills: #SoCVerification #CTestCases Description: Proficient in SoC verification and writing 'C' test cases for SoC DV. DFT Sr Engineer/Lead (5+ yrs, Bangalore) Skills: #DFTArchitectures #JTAG #ScanCompression #SynopsysTools Description: Understanding of DFT architectures like JTAG, Scan Compression Techniques, Synopsys tool experience. Physical Design (PD) (5-8 yrs, Bangalore) Skills: #Synthesis #PlaceAndRoute #CTS #TimingConvergence #IREMChecks #DRCLVSClosure #Innovus #FusionCompiler Description: Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks, and signoff DRC/LVS closure. Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM. Experience with Innovus tool is preferred, and a mix of Fusion Compiler & Innovus. IP DV (7+ yrs, Bangalore) Skills: #SV #UVM #IPVerification #DebuggingSkills Description: Proficient in SV/UVM based IP verification with good debugging skills. STA/Lead (8+ yrs, Bangalore) Skills: #TimingClosure #STA #ConstraintDevelopment #DFTConstraints Description: Well versed with timing closure (STA), timing closure methodologies, pre/post-layout constraint development to timing closure, handshake with the design team, and develop functional/DFT constraints. PCIE DV Lead (7+ yrs, Bangalore) Skills: #NetworkingProtocol Description: Experience on networking protocol. Analog Layout (6+ yrs, Bangalore/Hyderabad) Skills: #LowerNodes #FinfetTechnologies Description: Proficient in lower nodes and Finfet technologies. RTL Design Lead (8+ yrs, Bangalore) Skills: #PerlScripting #Lint #CDC #UPF #Constraints Description: Experience in Perl scripting, lint, CDC, UPF, constraints. Emulation (5+ yrs, Bangalore) Skills: #HAPS #Veloce #Palladium #Design #FPGA Description: Experience with HAPS, Veloce, Palladium, design, and FPGA. PDN (3-8 yrs, Bangalore) Skills: #EMIR #IRDrop #Redhawk Description: Experience with EMIR, IR Drop, Redhawk. Backend Power Optimization (3-8 yrs, Bangalore) Skills: #PTPX Description: Proficient in PTPX. PD CAD (3-5 yrs, Bangalore) Skills: #FusionCompiler Description: Experience with Fusion Compiler. FPGA (8-12 yrs, Hyderabad) Skills: #Coding #Validation #Verilog #C Description: Experience in coding, validation, Verilog, and C. Feel free to reach out for more details. Let's connect the right talent with the right opportunities! 🌟 #Hiring #JobOpenings #EngineeringJobs #BangaloreJobs #HyderabadJobs #ShortNoticeHiring

#hiring Senior Principal Engineer - Signoff, San Jose, United States, fulltime #jobs #jobseekers #careers #SanJosejobs #Californiajobs #Engineering Apply: https://lnkd.in/gKsVPi-V Job Overview: Arm has formed a new group to develop outstanding silicon demonstrators based on Arm's IP compute sub-system solutions and addressing markets such as premium mobile, infrastructure and automotive. Using the latest nodes, e.g. 3nm today, and applying the latest SoC 2.5D and 3D technology, Arm's ambition is to demonstrate industry outstanding performance by architecting, designing, implementing, and fabricating innovative silicon chips. Responsibilities: Your responsibilities will involve developing challenging electrical signoff methodologies. These methodologies will balance accuracy and yield on silicon. The following are the immediate challenges we will be working on as a team: We will develop a Static Timing Analysis flow that is standardized and is usable by all silicon groups within Arm We will work on strengthening our methodologies to analyze static and dynamic IR drop on the SoC. We will release a qualified flow that enable STA with back annotated voltage Electromigration analysis at the SoC level is another key responsibility of this role. Including Local thermal effects as part of electromigration analysis is a key criteria! Soft Error rate is a key concern for Infrastructure and Automotive SoC's. We will develop methodologies to analyze and alleviate the impact of Soft Error rate on SoC's Required Skills and Experience : Experience in developing Signoff methodologies such as Aging, STA, EM IR in advanced process nodes. Experience in collaborating across silicon engineering groups in your organization as well as with EDA vendors Work experience in Physical Implementation and Signoff methodologies Must have worked on methodology development on 5nm or 3nm technologies Strong data analysis skills to fetch data, analyze and provide practical insights "Nice To Have" Skills and Experience : Masters in Electrical Engineering Strong coding skills in Python or R or an equivalent language Strong presentation skills Salary Range From $2 46,925.00 To $ 319,550.00 We value people as individuals and our commitment is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process. In Return: We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

#hiring Senior Principal Engineer - Signoff, San Jose, United States, fulltime #jobs #jobseekers #careers #SanJosejobs #Californiajobs #Engineering Apply: https://lnkd.in/gKsVPi-V Job Overview: Arm has formed a new group to develop outstanding silicon demonstrators based on Arm's IP compute sub-system solutions and addressing markets such as premium mobile, infrastructure and automotive. Using the latest nodes, e.g. 3nm today, and applying the latest SoC 2.5D and 3D technology, Arm's ambition is to demonstrate industry outstanding performance by architecting, designing, implementing, and fabricating innovative silicon chips. Responsibilities: Your responsibilities will involve developing challenging electrical signoff methodologies. These methodologies will balance accuracy and yield on silicon. The following are the immediate challenges we will be working on as a team: We will develop a Static Timing Analysis flow that is standardized and is usable by all silicon groups within Arm We will work on strengthening our methodologies to analyze static and dynamic IR drop on the SoC. We will release a qualified flow that enable STA with back annotated voltage Electromigration analysis at the SoC level is another key responsibility of this role. Including Local thermal effects as part of electromigration analysis is a key criteria! Soft Error rate is a key concern for Infrastructure and Automotive SoC's. We will develop methodologies to analyze and alleviate the impact of Soft Error rate on SoC's Required Skills and Experience : Experience in developing Signoff methodologies such as Aging, STA, EM IR in advanced process nodes. Experience in collaborating across silicon engineering groups in your organization as well as with EDA vendors Work experience in Physical Implementation and Signoff methodologies Must have worked on methodology development on 5nm or 3nm technologies Strong data analysis skills to fetch data, analyze and provide practical insights "Nice To Have" Skills and Experience : Masters in Electrical Engineering Strong coding skills in Python or R or an equivalent language Strong presentation skills Salary Range From $2 46,925.00 To $ 319,550.00 We value people as individuals and our commitment is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process. In Return: We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.