The performance bottleneck of modern compute systems is often the I/O throughput of internal memory and external storage. Consequently, Siemens proactively partners with customers to help them scale-up and innovate their storage interface protocol design and verification (D&V) flows to address this challenge.
If you are in this segment of the D&V world, join us at the Future of Memory and Storage conference – #FMS2024 – this coming August 6-8 at the Santa Clara Convention Center.
Our technical experts will be at booth 1051, and they will also be presenting the following conference papers:
Verification Challenges and Solutions for Multi-Die Systems (UCIe) -- Prashant Dixit
in the session “UCIC-101-1: UCIe Solution Technology Innovations”
Tuesday, August 6, 8:30am – 9:35am, Ballroom G, Floor 1
Accelerating Verification of Computational Storage Designs (NVMe) -- Ujjwal Negi, Prashant Dixit
in the session “COMP-102-1: CS Solution/Technology Innovations”
Tuesday, August 6, 9:45am – 10:50am, Ballroom C, Floor 1
Conference Agenda: https://sie.ag/6ytL9x
Registration: https://sie.ag/6zdbu6
Join us!