Mohammad Tahmid Hassan’s Post

🔔 DAY-9: Look A head Carry adder #100daysofrtl 🚀 Unveiling Speed in Binary Addition: The Ripple Carry Adder Circuit! 💻 Ever wondered how computers swiftly crunch numbers? Enter the realm of digital circuits with the Ripple Carry Adder, a high-speed warrior in binary arithmetic. 🧮 Ripple Carry Adder Highlights: Combines multiple Full Adders for efficient binary addition. Implements a simple carry propagation mechanism. 👨💻GitHub Repository: https://lnkd.in/gBzN2j5N #vlsi #verilog #digitalelectronics #100daysofrtl #vlsidesign #vlsitraining

Hello Linkedin fam, continuing my learning about chip designing and large scale integration sharing my progress of Day 2 with you all. Day 2: Use of multiplexer to make a calculator which is capable of performing basic arithmetic operations such as addition,substraction,multiplication and division. The select line $op[1:0] acts to select which operation will be performed coded in TL-Verilog and IDE used : Makerchip. #TLVerilog #Verilog #hardware #chipdesigning

🚀Day 36 of the #100daysRTLChallenge 🚀. Today I worked on " Dual Port Random Access Memory (RAM) ".I also created a 1KB of this memory(RAM) . 🤔 When & why Dual Port RAM is used ? : 1. Asynchronous multiprocessor systems require a means to transmit data between two independently running processors. 2. Dual port memory provides a common memory accessible to both processors that can be used to share and transmit data and system status between the two processors. I am sharing my repository where I place all my work till now.check it out here https://lnkd.in/g8_wT3zi Feel free to follow, connect and start learning with me 😊 #digitaldesign #verilog #vlsi #digitallogic #PublicLearning #EngineeringJourney #digitalelectronics #hdlLearning

🌍 In a not-so-distant future, the fight against #climate #change brings forth the EcoMender Bot, a #marvel of #innovation built to #sustain our #planet. Powered by #FPGA, it swiftly navigates through industries, identifying inefficiencies and restoring balance. Ready to build the #future? 🌱🤖 This theme teaches advanced concepts of #FPGA, #Verilog and #CPUArchitecture through software such as #Intelquartus and #risc5 #toolchains.

Last week, I re-read an introduction to the AXI4 Protocol and I learned a lot! I enjoy revisiting specifications because they often help help fill gaps in my initial (and forgotten) understanding. I downloaded an AXI4 introduction from ARM which helped me refresh several concepts: • Atomic accesses • Unaligned transfers • Exclusive accesses • Transaction flows (I had forgotten that the first beat of write data can come before the AW transfer - and is legal) I wish AXI specs also used the time-space diagrams like the CHI specifications—they’re super helpful. By the way, I always forget how the ACE Cache states map to the more familiar MOESI protocol so I thought I’d share it here! How do you remember this? #rtldesign #verilog #riscv #servingTheNextBug #lowpowerdesign #verification #semiconductors #verificationengineer

🚀 Excited to Share My 39th YouTube #techshort! 🚀 In this tech short, learn how to write a function in SystemVerilog that cyclically rotates an array clockwise by one position. Array rotation is a fundamental operation often needed in various algorithms and VLSI applications. Let's dive into how we can accomplish this in a clear, efficient way! 🔔 Don't forget to like, share, and subscribe for more tech shorts! #vlsi #verification #semiconductors #verilog #systemverilog #asic #designverification #interviewpreparation #constraints #uvm #podcastwithnavneet #navneettechshorts #navneettechquiz #staytuned📚

SETUP AND HOLD TIME Setup Time: Setup Time is the minimum time the data signal should be held stable before the clock arising, so data is easily sampled by the clock Hold Time: Hold time is the minimum time the data signal should be held stable after the clock arising, so data are reliably sampled. For violation free circuit: 1. Min delay of combinational path > Hold time of capture FF 2. Max delay of combinational path < clock period - setup time of capture FF #rtl #fpga #systemverilog #setupandholdtime #setuptime #holdtime #verilog #vlsi #timeviolations

Introducing Open-Binius! 🚀 "Hardware IPs for accelerating ZK proofs over binary fields" Open-source (MIT) FPGA code. A community effort with academia. Check out our initial results in the table below. LFG! 🔗Github Repo: in first comment 👇 #opensource #zkp

Day-23: Edge Detectors ✨Hello LinkedIn Community! As part of my #100daysofrtl challenge, I've designed Edge Detectors using #verilog. These were simulated on #xilinxvivado. An edge detector is a digital circuit that detects transitions in a signal, such as a rising or falling edge. Edge detectors are commonly used in applications such as clock synchronization, data sampling, and digital communication. Here, I've implemented posedge, negedge and either edge detectors. Checkout my Github repository here https://lnkd.in/gZJ-9-_C #100DaysOfRTL #Verilog #DigitalDesign #HardwareEngineering #LearningJourney

Day-22: Ring & Johnson Counters ✨Hello LinkedIn Community! As part of my #100daysofrtl challenge, I've designed Ring counter and johnson Counter using #verilog. These were simulated on #xilinxvivado. ⫸ A Ring counter is a typical application of the Shift register. The only change is that the output of the last flip-flop is connected to the input of the first flip-flop in the case of the ring counter but in the case of the shift register it is taken as output. A straight ring counter is also known as one-hot counter. ⫸ In Johnson counter, the complemented output of last flip flop is connected to input of first flip flop. It is formed by the feedback of the output to its own input. Johnson counter is a ring with an inversion. Another name of Johnson counter are: creeping counter, twisted ring counter, walking counter, mobile counter. Checkout my Github repository here https://lnkd.in/gZJ-9-_C #100DaysOfRTL #Verilog #DigitalDesign #HardwareEngineering #LearningJourney