Moshe Zalcberg’s Post

In #SNUGIsrael's second keynote presentation, Google’s Uri Frank explained why the AI-era silicon challenges are much different than we had in the past. For start, AI models require a x10 speedup in compute power every year, much more than Moore's law.   Therefore, the current design flow that requires an average of 3 years for a new major device won’t cut. By the time these chips are ready, the workloads they were planned for are no longer relevant! Uri said that an #evolution won’t be enough- like the #AI-based small improvements offered by the EDA vendors. We need a #revolution - we must define new ways of designing chips:  “What if designing a custom chip took a few people a few weeks?” he asked. Synopsys Users Group (SNUG)

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The keynote sounded like: We better be young, healthy and rich. Then design will take weeks. On another note - A friend once observed: "the theoretical limit to reducing project schedule, is when meetings will collide back to back". Once the slogan for productivity was "reuse!". Reusing old irrelevant designs kinda made it less attractive. Now the slogan is "chiplets". maybe, Who knows?

Ishay Beery

Applied Scientist at Amazon prime video sport

2mo

Are there any answers to these questions?

Avi Yagodnick

VLSI Design Verification Engineer

2mo

Interesting to see the "3-years rule" for a project still holds for so many years, where 40%-50% of time is from tapeout and on... (depending how much time invested in the exploration/arch stage).

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