Mahmoud Wafa’s Post

⏳ Design Verification: The Final Countdown to Tapeout! ⏳ Ah, the life of a verification engineer… where the real fun begins when RTL passes and gate-level simulation (GLS) enters the chat. 😬 • You start with RTL, confident… until GLS hits you with timing violations and X-propagation issues. The SDF is more of a mystery novel than a file 📚. • Then comes the tapeout deadline looming on the horizon, and suddenly, every clock cycle feels like it’s on a stopwatch. 🏃♂️ • Sign-off stage? Let’s just say it’s where verification engineers test their speed and sanity—hunting down those last-minute glitches while juggling coverage reports and hoping that no sneaky bug shows up in the final netlist. 🤯 • And when that magical sign-off happens, it’s not just a project milestone. It’s a victory over timing, logic, and the universe itself! 🌟 But hey, who needs sleep when the thrill of meeting tapeout keeps you going? 😉 Kudos to everyone living this rollercoaster! Here’s to hitting those sign-off deadlines, closing the timing loops, and ensuring that the silicon dream becomes a reality. #designverification #gatelevelsimulation #tapeoutmadness #vlsi #signoffstage #verificationengineer #techhumor #weekendpost

Want to work as a Design & Verification Engineer ? In this video we have discussed ->The skills required to become a professional design & verification engineer. ->Vast opportunities in Design & Verification ->Who should opt for Design & Verification domain? **REGISTRATION OPEN for upcoming Design & Verification Course. (Link in comments) If you have any questions, feel free to ask them in comments.

5 Mistakes I made as a Verification Engineer Someone recently asked me about my experience working as a Verification engineer and if I have any advice to share to engineers starting now. I thought it would be better if I shared some of the silly mistakes I made back then. These are things I’ve learned to improve over time especially points 2 and 5 - which weren’t very clear to me at first. I still remember filing bugs without going too deep in the RTL and sometimes getting my analysis completely wrong. I also used to delete passing logs and coverage files too soon - struggling to provide results later when asked. Does this sound relatable? I’m sure you’ve made your own mistakes—comment below! 😄 #servingTheNextBug #lowpowerdesign #verification #semiconductors #verificationengineer

Hi everyone, I started a new lecture series on YouTube focused on formal verification. It's been over a week, and I'm posting every day about one or another topic on formal verification. Sharing the progress on my YouTube lecture series focused on formal verification using Jasper Gold: Understanding Formal Verification and Writing Assertions and Assumptions Link: Watch here(https://lnkd.in/gEetWpVe) Exploring Reusable Property Based Verification Link: Watch here(https://lnkd.in/gF8gCYu7) Creating Effective Test Bench Files with SystemVerilog Assertions (SVA) Link: Watch here (https://lnkd.in/gMvgGwzs) FSM Deadlock and Livelock Testing Insights Link: Watch here(https://lnkd.in/g8TCDYtk) Coverage Analysis in the Verification Process Link: Watch here(https://lnkd.in/g8TCDYtk) Utilizing Xprop Verification App and How to Use It Link: Watch here(https://lnkd.in/g_W9NSbT) Mastering Formal verification complete FPV based verification flow: Watch here (https://lnkd.in/giaQq7em) These tutorials aim to empower individuals interested in digital design verification, covering both functional and formal aspects — two key areas in verification. A heartfelt thank you to Ram Mantha, Carl Harvey, Kenny Chan, and Rohit Menon for the opportunities that have fueled this journey. Grateful for the unwavering support from the community. Special acknowledgment to Yashwanth Chandrappa Shobha and Vrit Raval for their support, whenever needed. 🎙️ Join the Ongoing Conversation: This is more than a playlist; it's an ongoing lecture series! Have questions, insights, or simply want to connect? Feel free to drop your thoughts in the comments section of each video. Let's turn this into a dynamic learning space! 🔗 Watch the entire playlist here(https://lnkd.in/gDbR2RKY) Let's continue exploring the fascinating realm of Digital Design verification together! Thank you guys!! 🌐✨ #FormalVerification #DigitalDesign #HardwareVerification #YouTubeTutorials #Engineering #KnowledgeSharing #DigitalSystems #ASIC #FPGA #VerificationEngineering

𝐔𝐕𝐌: 𝐔𝐩 𝐘𝐨𝐮𝐫 𝐕𝐞𝐫𝐢𝐟𝐢𝐜𝐚𝐭𝐢𝐨𝐧 𝐆𝐚𝐦𝐞 - 2024'𝐬 𝐇𝐨𝐭𝐭𝐞𝐬𝐭 𝐓𝐫𝐞𝐧𝐝𝐬 (𝐚𝐧𝐝 𝐖𝐡𝐲 𝐘𝐨𝐮 𝐒𝐡𝐨𝐮𝐥𝐝 𝐂𝐚𝐫𝐞!) 𝐂𝐚𝐥𝐥𝐢𝐧𝐠 𝐚𝐥𝐥 𝐀𝐒𝐈𝐂 𝐯𝐞𝐫𝐢𝐟𝐢𝐜𝐚𝐭𝐢𝐨𝐧 𝐫𝐨𝐜𝐤𝐬𝐭𝐚𝐫𝐬! Ready to take your chip validation to the next level? Buckle up, because the latest updates in UVM are here to blow your socks off! 𝐁𝐞𝐞𝐧 𝐬𝐭𝐮𝐜𝐤 𝐢𝐧 𝐭𝐡𝐞 𝐔𝐕𝐌 1.2 𝐫𝐮𝐭? Don't sweat it! UVM 3.0 just dropped, packing heat like: 𝐈𝐦𝐩𝐫𝐨𝐯𝐞𝐝 𝐜𝐨𝐧𝐟𝐢𝐠𝐮𝐫𝐚𝐛𝐢𝐥𝐢𝐭𝐲: Customize your verification environment with ease, thanks to enhanced configuration options. Say goodbye to code spaghetti! 𝐒𝐭𝐫𝐞𝐚𝐦𝐥𝐢𝐧𝐞𝐝 𝐜𝐨-𝐬𝐢𝐦𝐮𝐥𝐚𝐭𝐢𝐨𝐧: Integrate seamlessly with formal tools for more comprehensive coverage and bug hunting. Formal verification ain't scary anymore! 𝐅𝐚𝐬𝐭𝐞𝐫, 𝐦𝐨𝐫𝐞 𝐞𝐟𝐟𝐢𝐜𝐢𝐞𝐧𝐭: Experience blazing-fast simulations with performance optimizations under the hood. Time is money, people! ⌚️ 𝐁𝐮𝐭 𝐰𝐚𝐢𝐭, 𝐭𝐡𝐞𝐫𝐞'𝐬 𝐦𝐨𝐫𝐞! The UVM community is buzzing with innovation: ✨ 𝐀𝐝𝐯𝐚𝐧𝐜𝐞𝐝 𝐚𝐬𝐬𝐞𝐫𝐭𝐢𝐨𝐧 𝐭𝐞𝐜𝐡𝐧𝐢𝐪𝐮𝐞𝐬: Uncover subtle design flaws with powerful new assertion methodologies. Bugs beware! ✨ 𝐂𝐨𝐯𝐞𝐫𝐚𝐠𝐞 𝐠𝐫𝐨𝐮𝐩𝐬 2.0: Elevate your coverage game with improved flexibility and control. Leave no corner untested! ️♀️ ✨ 𝐅𝐨𝐫𝐦𝐚𝐥 𝐯𝐞𝐫𝐢𝐟𝐢𝐜𝐚𝐭𝐢𝐨𝐧 𝐢𝐧𝐭𝐞𝐠𝐫𝐚𝐭𝐢𝐨𝐧: Formalize your UVM for ultra-high confidence verification. Sleep soundly at night! 𝐑𝐞𝐚𝐝𝐲 𝐭𝐨 𝐥𝐞𝐯𝐞𝐥 𝐮𝐩 𝐲𝐨𝐮𝐫 𝐀𝐒𝐈𝐂 𝐯𝐞𝐫𝐢𝐟𝐢𝐜𝐚𝐭𝐢𝐨𝐧 𝐠𝐚𝐦𝐞? Hit that like button, share with your network, and let's discuss in the comments! https://lnkd.in/g8uYqfD #UVM #ASICVerification #VerificationEngineer #ChipDesign #FormalVerification #Coverage #Innovation #theartofverification

Are ASIC verification freshers learn sv and uvm verifciation Env 🧪 Develop UVM Testbench Components 🔧 Create not_gate_sequence_item 🔄 Implement not_gate_sequencer 🎭 Design not_gate_driver 👀 Develop not_gate_monitor ✅ Build not_gate_scoreboard 🏗️ Construct not_gate_agent 🌐 Assemble not_gate_env 📝 Write Test Scenarios 🔬 Develop Basic Functionality Test 🔁 Create Toggle Test ⏱️ Design Timing Test 🛠️ Implement UVM Test 🧪 Code not_gate_test 🏃♂️ Create UVM Test Runner 🚀 Develop top.sv 📊 Develop Functional Coverage 📈 Implement not_gate_coverage 🔍 Add Assertions ⚠️ Code not_gate_assertions 🖥️ Set Up Simulation Environment 📜 Create simulation script 🔧 Configure simulator settings 🚀 Run Simulations 🏁 Execute test cases 📊 Collect coverage data 📈 Analyze Results 📊 Review coverage reports 🐛 Debug any issues 📝 Document Findings 📄 Create test report 📊 Summarize coverage results 🔄 Iterate and Refine 🔧 Optimize testbench if needed 🧪 Add additional test cases if required                                             https://lnkd.in/gZhA6bGY

✅ UVM Testbench Flow for Counter Design ✅ Verification is a critical part of the hardware design process, ensuring that our designs meet the required functionality before deployment. Today, I’d like to share insights on the UVM Testbench Flow for Counter Design. 🔑 Key Components: UVM Testbench Top: Instantiates the DUT (Design Under Test) and interfaces. We connect clock and reset, handle signals, and trigger the test using run_test(). UVM Environment: Contains the agents and scoreboards to ensure structured hierarchy and verification checks. UVM Agent: Comprises the driver, monitor, and sequencer. This modular approach allows reusable components and flexible configurations for different interfaces. UVM Sequences: These generate the stimulus, randomized and constrained to meet the functional requirements. Sequences are sent to the driver for pin-level activity. UVM Scoreboard: This component plays a pivotal role in comparing actual DUT outputs with the expected reference model outputs, ensuring functional correctness. 🔗Execute the Complete Code here: https://lnkd.in/gxWaD2bg 👉👉 For more hands on Projects, Protcols Verification using SV, UVM Do follow Prasanthi Chanda Special thanks to Jairaj Mirashi

𝐔𝐕𝐌: 𝐔𝐩 𝐘𝐨𝐮𝐫 𝐕𝐞𝐫𝐢𝐟𝐢𝐜𝐚𝐭𝐢𝐨𝐧 𝐆𝐚𝐦𝐞 - 2024'𝐬 𝐇𝐨𝐭𝐭𝐞𝐬𝐭 𝐓𝐫𝐞𝐧𝐝𝐬 (𝐚𝐧𝐝 𝐖𝐡𝐲 𝐘𝐨𝐮 𝐒𝐡𝐨𝐮𝐥𝐝 𝐂𝐚𝐫𝐞!) 𝐂𝐚𝐥𝐥𝐢𝐧𝐠 𝐚𝐥𝐥 𝐀𝐒𝐈𝐂 𝐯𝐞𝐫𝐢𝐟𝐢𝐜𝐚𝐭𝐢𝐨𝐧 𝐫𝐨𝐜𝐤𝐬𝐭𝐚𝐫𝐬! Ready to take your chip validation to the next level? Buckle up, because the latest updates in UVM are here to blow your socks off! 𝐁𝐞𝐞𝐧 𝐬𝐭𝐮𝐜𝐤 𝐢𝐧 𝐭𝐡𝐞 𝐔𝐕𝐌 1.2 𝐫𝐮𝐭? Don't sweat it! UVM 3.0 just dropped, packing heat like: 𝐈𝐦𝐩𝐫𝐨𝐯𝐞𝐝 𝐜𝐨𝐧𝐟𝐢𝐠𝐮𝐫𝐚𝐛𝐢𝐥𝐢𝐭𝐲: Customize your verification environment with ease, thanks to enhanced configuration options. Say goodbye to code spaghetti! 𝐒𝐭𝐫𝐞𝐚𝐦𝐥𝐢𝐧𝐞𝐝 𝐜𝐨-𝐬𝐢𝐦𝐮𝐥𝐚𝐭𝐢𝐨𝐧: Integrate seamlessly with formal tools for more comprehensive coverage and bug hunting. Formal verification ain't scary anymore! 𝐅𝐚𝐬𝐭𝐞𝐫, 𝐦𝐨𝐫𝐞 𝐞𝐟𝐟𝐢𝐜𝐢𝐞𝐧𝐭: Experience blazing-fast simulations with performance optimizations under the hood. Time is money, people! ⌚️ 𝐁𝐮𝐭 𝐰𝐚𝐢𝐭, 𝐭𝐡𝐞𝐫𝐞'𝐬 𝐦𝐨𝐫𝐞! The UVM community is buzzing with innovation: ✨ 𝐀𝐝𝐯𝐚𝐧𝐜𝐞𝐝 𝐚𝐬𝐬𝐞𝐫𝐭𝐢𝐨𝐧 𝐭𝐞𝐜𝐡𝐧𝐢𝐪𝐮𝐞𝐬: Uncover subtle design flaws with powerful new assertion methodologies. Bugs beware! ✨ 𝐂𝐨𝐯𝐞𝐫𝐚𝐠𝐞 𝐠𝐫𝐨𝐮𝐩𝐬 2.0: Elevate your coverage game with improved flexibility and control. Leave no corner untested! ️♀️ ✨ 𝐅𝐨𝐫𝐦𝐚𝐥 𝐯𝐞𝐫𝐢𝐟𝐢𝐜𝐚𝐭𝐢𝐨𝐧 𝐢𝐧𝐭𝐞𝐠𝐫𝐚𝐭𝐢𝐨𝐧: Formalize your UVM for ultra-high confidence verification. Sleep soundly at night! 𝐑𝐞𝐚𝐝𝐲 𝐭𝐨 𝐥𝐞𝐯𝐞𝐥 𝐮𝐩 𝐲𝐨𝐮𝐫 𝐀𝐒𝐈𝐂 𝐯𝐞𝐫𝐢𝐟𝐢𝐜𝐚𝐭𝐢𝐨𝐧 𝐠𝐚𝐦𝐞? Hit that like button, share with your network, and let's discuss in the comments! https://lnkd.in/g8h5b-_E #UVM #ASICVerification #VerificationEngineer #ChipDesign #FormalVerification #Coverage #Innovation #theartofverification

𝙑𝙀𝙍𝙄𝙁𝙄𝘾𝘼𝙏𝙄𝙊𝙉 𝘿𝙄𝘼𝙍𝙄𝙀𝙎 #2 📖 📒 📓 I asked Momcilo Kovrlija, one of our verification team leaders here at Vtool - Smart Verification and a UVM expert, what advanced UVM feature he loves the most. "𝐌𝐲 𝐟𝐢𝐫𝐬𝐭 𝐩𝐢𝐜𝐤 𝐰𝐨𝐮𝐥𝐝 𝐝𝐞𝐟𝐢𝐧𝐢𝐭𝐞𝐥𝐲 𝐛𝐞 𝐮𝐯𝐦_𝐜𝐚𝐥𝐥𝐛𝐚𝐜𝐤'𝐬. 𝐓𝐡𝐞 𝐬𝐡𝐞𝐞𝐫 𝐚𝐦𝐨𝐮𝐧𝐭 𝐨𝐟 𝐯𝐞𝐫𝐬𝐚𝐭𝐢𝐥𝐢𝐭𝐲 𝐩𝐫𝐨𝐯𝐢𝐝𝐞𝐝 𝐰𝐢𝐭𝐡 𝐭𝐡𝐞𝐢𝐫 𝐮𝐬𝐚𝐠𝐞 𝐜𝐚𝐧 𝐢𝐦𝐩𝐫𝐨𝐯𝐞 𝐭𝐡𝐞 𝐪𝐮𝐚𝐥𝐢𝐭𝐲 𝐨𝐟 𝐭𝐡𝐞 𝐞𝐧𝐯𝐢𝐫𝐨𝐧𝐦𝐞𝐧𝐭 𝐬𝐢𝐠𝐧𝐢𝐟𝐢𝐜𝐚𝐧𝐭𝐥𝐲. 𝐖𝐡𝐞𝐧 𝐢𝐦𝐩𝐥𝐞𝐦𝐞𝐧𝐭𝐞𝐝 𝐢𝐧 𝐜𝐨𝐫𝐫𝐞𝐜𝐭 𝐩𝐥𝐚𝐜𝐞𝐬, 𝐚𝐧𝐝 𝐢𝐧 𝐚 𝐜𝐨𝐫𝐫𝐞𝐜𝐭 𝐰𝐚𝐲, 𝐩𝐨𝐬𝐬𝐢𝐛𝐢𝐥𝐢𝐭𝐢𝐞𝐬 𝐠𝐚𝐢𝐧𝐞𝐝 𝐭𝐨 𝐭𝐰𝐞𝐚𝐤 𝐭𝐡𝐞 𝐞𝐧𝐯𝐢𝐫𝐨𝐧𝐦𝐞𝐧𝐭 𝐚𝐫𝐞 𝐞𝐧𝐝𝐥𝐞𝐬𝐬." Stay tuned for more stories to come. #verificationengineer #verification #uvm #stories ---------------------------------------- In this series, I am asking verification engineers about various aspects of their jobs. My hope is that their stories will inspire more people to truly appreciate how the job of verification engineer is interesting, challenging, and, at the end of the day, very fulfilling.

Helpful for those who want to understand indepth about the communication between driver and sequencer.