Pragnesh Patel’s Post

Greetings! This announcement was a long time due but I feel really proud to announce that my 1st first-author paper titled "LogGen: A Parameterized Generator for Designing Floating-Point Logarithm Units for Deep Learning" was accepted and presented at The 23rd International Symposium on Quality Electronic Design (ISQED'22). The conference was held from April 6-8 2022, but due to Covid19, the paper was presented virtually. I am thankful to Aman Arora for his constant support throughout. I am also thankful to Dr. Lizy John, Dr. Earl Swartzlander and the The University of Texas at Austin for providing me the guidance and resources needed to successfully execute this project. In short, LogGen is an open-source, parameterized generator for generating logarithm unit implementations in Verilog that are optimized for smaller floating-point datatypes like bfloat16, IEEE half-precision and tensorfloat-32. LogGen enables generation of designs by varying multiple knobs - datatype, accuracy, base of logarithm, storage, and latency. It uses a flexible and efficient Look-Up Table (LUT) based architecture that leverages the small size of datatypes to optimize this architecture. The Github repo for the LogGen can be found here - https://lnkd.in/gpse-Twi. If you are interested to know more, this is the link to the paper- https://lnkd.in/gGUTk7r6 The following is a link to a short Youtube video summarizing our work & results- https://lnkd.in/gxZ44fYE #floatingpoint #opensource #hardware #logarithm #isqed #deeplearning #dl #vlsi #verilog #hardware #research #publication #utaustin