SiMaxTech Pvt Ltd’s Post

🚀🧠 Calling all tech wizards and engineering superheroes! 💻✨ Are you tired of scrolling through cat memes and dreaming of a job where your brainpower can really shine? Well, dust off your cape because we've got some exciting news! 🦸♂️🦸♀️ 🔍 We're on the lookout for: 🔹 STA Engineer - Whether you can spot a bug from a mile away or you're a pro at untangling those tricky design knots, we want YOU! 🔹 Analog Layout Engineer - If you can turn circuitry into a work of art and have a knack for precision, join us in crafting the future of technology! 🔹 Verification Engineer - Calling all code-crackers and problem-solvers! If you thrive on uncovering the mysteries of digital design, we've got the perfect mission for you! 📍 Locations: Bangalore and Hyderabad - because who says the best jobs are only in Silicon Valley? So, if you've got 4 to 15 years of experience under your utility belt (or even 3 to 8 for our Analog Layout wizards), don't wait! 🚀 Shoot your resume over to careers@smartsocs.com and let's make some magic together! 💫 #SmartSoC #Engineers #Verification #Analog #Layout #STA #JoinTheSmartSide #TechTalentWanted

🚀🧠 Calling all tech wizards and engineering superheroes! 💻✨ Are you tired of scrolling through cat memes and dreaming of a job where your brainpower can really shine? Well, dust off your cape because we've got some exciting news! 🦸♂️🦸♀️ 🔍 We're on the lookout for: 🔹 STA Engineer - Whether you can spot a bug from a mile away or you're a pro at untangling those tricky design knots, we want YOU! 🔹 Analog Layout Engineer - If you can turn circuitry into a work of art and have a knack for precision, join us in crafting the future of technology! 🔹 Verification Engineer - Calling all code-crackers and problem-solvers! If you thrive on uncovering the mysteries of digital design, we've got the perfect mission for you! 📍 Locations: Bangalore and Hyderabad - because who says the best jobs are only in Silicon Valley? So, if you've got 4 to 15 years of experience under your utility belt (or even 3 to 8 for our Analog Layout wizards), don't wait! 🚀 Shoot your resume over to mohammed.ismail@smartsocs.com and let's make some magic together! 💫 #SmartSoC #Engineers #Verification #Analog #Layout #STA #JoinTheSmartSide #TechTalentWanted

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Hi Connections, #SpanIdea System Immediately Hiring, #FPGA  Design Engineer #Experience:Strictly 2-10 Yrs Location: Hyderabad PFA JD: Hi Connections, #SpanIdea System Immediately Hiring, #RTL Design Engineer #Experience:Strictly 2-8Yrs Location: Hyderabad PFA JD: Setup ASIC QA flows for RTL design quality checks. Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains. Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps. Advocate clock constraints, false paths, multi-cycle paths, IO delays, exceptions, and waivers. Checking the flow errors, design errors & violations and reviewing the reports. Debugging CDC, RDC issues and propose the RTL fixes. Supporting DFX team for DFX controller integration, Scan insertion, MBIST insertion and DFT DRC & MBIST checks. Handling multiple PNR blocks, building wrappers and propagating constraints, waivers, etc. Flows or Design porting to different technology libraries. Generating RAMs based on targeted memory compilers and integrating with the RTL. Familiar with the functional verification simulations. Interested PPL Share your Resume to vandanab@spanidea.com or Contact me - 7975278067

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Greetings from 𝗪𝗮𝗳𝗲𝗿𝗠𝗮𝘁𝗿𝗶𝘅 team, we are actively hiring the following positions: Interested candidates share your resume to 𝗵𝗿@𝘄𝗮𝗳𝗲𝗿𝗺𝗮𝘁𝗿𝗶𝘅.𝗰𝗼𝗺 𝟭) 𝗗𝗙𝗧 :3 to 10 Years  Skill Set :  Hands on experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Full chip level. Should have good knowledge about all DFT concepts Scan insertion and validation, BIST, LBIST, MBIST insertion and validation, ATPG and Pattern Validation w/wo Timing, DFT mode timing Analysis and sign off. Understanding of DFT architectures like Boundary scan (JTAG), Scan Compression Techniques (XOR, Adaptive, OP-MISR etc.), scan chain insertion and verification. Must have experience generating scan patterns and coverage statistics for various fault models like stuck at (Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories (E-fuse etc.). Experience in Coverage Analysis.   𝟮)𝗔𝗻𝗮𝗹𝗼𝗴 𝗟𝗮𝘆𝗼𝘂𝘁 – 𝟱+ 𝗬𝗲𝗮𝗿𝘀 𝗼𝗳 𝗲𝘅𝗽𝗲𝗿𝗶𝗲𝗻𝗰𝗲 Skill Set:  Good hands on experience in lower technology nodes like N3, N5 Working knowledge on DDR and SERDES kind of Ips Ability to lead few junior engineers for the successful execution Good tool knowledge on Cadence XL and Calibre verification Job Location : Bangalore 3)𝗠𝗲𝗺𝗼𝗿𝘆 𝗗𝗲𝘀𝗶𝗴𝗻 & 𝗠𝗲𝗺𝗼𝗿𝘆 𝗟𝗮𝘆𝗼𝘂𝘁 – 𝟱+ 𝗬𝗲𝗮𝗿𝘀 𝗼𝗳 𝗲𝘅𝗽𝗲𝗿𝗶𝗲𝗻𝗰𝗲. Hands on experience in custom memory and/or memory compiler design techniques and architectural tradeoffs like single versus dual rail, high density versus high performance, Vmin, performance, read/write assists etc. Ability to contribute technically as well as lead a team. Institute memory IP QA (quality assurance) audits/checks to ensure high quality IP deliveries. Strong familiarity with memory characterization and EDA view generation (timing, noise, power, Mbist etc.) process. #vlsi #al #pd #dv #dft #analoglayout #analogcircuit #physicaldesign #designverification #semiconductor #chip

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