Tessent Silicon Lifecycle Solutions’ Post

Introducing Tessent Hi-Res Chain software, a new tool from Siemens EDA, designed to address the critical challenges faced by integrated circuit (IC) design and manufacturing teams in advanced technology nodes, where even minor process variations can significantly impact yield and time-to-market. As IC designs progress to more advanced nodes at 5nm and below, they become increasingly susceptible to manufacturing variations that can create defects and slow yield ramp. At these geometries, traditional failure analysis (FA) methods can require weeks or months of laboratory effort to investigate. Siemens’ new Tessent Hi-Res Chain tool addresses this problem by rapidly providing transistor-level isolation for scan chain defects. For advanced process nodes where yield ramp heavily relies on chain diagnosis, the new software can boost diagnosis resolution by more than 1.5x, reducing the need for costly extensive failure analysis cycles. Read more about the new Tessent Hi-Res Chain software. https://sie.ag/tT8NP #TessentHiResChain #YieldLearning #yieldmanagement #TessentYieldInsight #DFTmarketleader #Tessent #semiconductor #SiemensEDA

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