Need for Faster Innovation in EDA Tools for Design/Verification

Long Chip Development Cycles

Even with advances in design automation, chip development cycles have not shrunk as much as they should have in the past 20 years. It still takes upwards of 2+ years to build complex networking or CPU/GPU chip from architecture specification to tape-out. The design cycles are even longer for chips/IPs designed from scratch. 

A typical ASIC flow has front-end (RTL design and verification) and back-end (physical implementation to create the final GDS) activities that happen in parallel. Each activity has a full slew of EDA tools to help accelerate different phases. 

While EDA companies have extensively used AI for back-end flows, specifically in floorplanning, placement, and routing (P & R), these techniques have yet to penetrate the front-end development. 

As you can see from the ASIC flow diagram, finalizing the chip/module floorplans is not usually in the long pole in ASIC development unless it is SOC and most IPs are reused. Investing too much in enhancing only that part of the flow will not help overall tape-out schedules as front-end activities will start gating the overall schedule. 

What can EDA vendors do for the design phase? 

The design phase involves micro-architecture specification of the modules followed by RTL coding where the designer translates that specification to RTL. The quality of the micro-architecture and the RTL depend heavily on the expertise of the designer. Poor design choices lead to overly complex designs that take a significantly larger time to converge. While some tools like RTL architect claim to give early feedback to designers on the design quality (timing, area, congestion, etc.), they do not compensate for the lack of expertise from the designer. 

There are many ways to improve the design phase of the project - by reusing large portions of the design or using readily available IPs (instead of reinventing the wheel every time), by making sure the architectural specifications are accurate and clearly specified, and by doing proper module assignments (based on the expertise of the design engineers) and enabling tight collaboration between design and verification engineers, etc. In this article, my main focus is on how EDA can further help in the design phase.

In the design phase, most of the EDA industry’s innovation is centered around creating tools that can help find low-level issues (lint/clock domain crossing, missing clock-gate opportunities, etc.) and fix them quickly. While these tools do help, most of the time, it is garbage in -> garbage out. If the quality of the RTL is not good to start with, there is only so much these tools can help in closing the design faster. 

That's where there is a need for tools that can read high-level abstraction (either architectural model or even plain English text specification) and create low-level pipelined RTL. There are already some tools like HLS (High-Level Synthesis) that can take C-model and churn out RTL, but they fail to converge on complex/large designs and need extensive guidelines from the user for pipelining. And the C-model itself could be buggy due to incorrect translation of the architectural specification.

If natural language processing (NLP) can be used to parse high-level architectural specifications (written in a specific tool-friendly format) and spit out RTL, that would be the ultimate game-changer! As with any innovation, it might take decades before such a fancy tool can beat the trained humans. But, I hope EDA vendors continue to invest in these futuristic tools which could one day become reality (like many unimaginable things that were made possible by AI)

Intermediately, vendors should also look into creating tools that can incrementally optimize the RTL code on their own - like optimizing buffer sizes and reshuffling logic between pipeline stages, removing redundant logic, adding fine-clock gating, etc. Some tools like Mentor PowerPro started providing fine-clock gating features but the RTL could be buggy with the onus on the designer to verify the quality of RTL with Formal analysis. 

Design Verification Improvements

The next big challenge is design verification. A critical bug has the potential to upset all the product planning. 

There have been many advances in the last two decades on the verification front.  SV/UVM has simplified test-bench creation and enabled the design verification (DV) community with a powerful tool called randomization. More and more DV engineers are relying on randoms (constrained randoms) to verify all functionality without any directed tests. While this approach can help verify 90% of the functionality of the module, without proper metrics, it is hard to conclude if all features are fully verified. DV starts to rely on functional coverage to determine if the test “intent is met”. 

What can EDA tool vendors do to make the design bug free faster? I think they should invest more in Formal verification and make the Formal tools scale to larger designs. The formal verification concept is extremely powerful - the tool does exhaustive mathematical analysis to check if the design satisfies a set of behaviors (as specified by assertions). It can catch corner-case bugs that are hard to catch with traditional stimuli-based verification. Unfortunately, as with any powerful tool, the run times are large, sometimes could take multiple days to check a single property, and designers often need to partition and feed a small portion of their module to the tool to verify some properties. This adds additional overhead. If these formal analysis tools can be enhanced with AI to handle large designs without exponentially increasing the complexity of their computation, they have the potential to replace the traditional simulation-based verification. 

Emulation is another way to get more clocks per cycle on any design. From being an “optional” thing a decade ago, it has become a “must-have” platform for all chip development. While this platform has many merits, it does not reuse any components from the simulation environments and requires completely new development. Some platforms do provide porting UVM test benches to emulation. But, run-time slows down significantly while doing so and the benefits of emulation start to wane. 

If EDA vendors could create a seamless integration of formal, simulation, and emulation methods for verification (where there is heavy re-use of infrastructure across them) that would change the verification landscape.

Summary

My request to EDA vendors - focus on drastic improvements in current tools/new offerings for cutting down the front-end phase of the chip design. Otherwise, no matter how much you improve the back-end tools, chip design cycles won’t see a significant reduction.