- CXL 3.2 provides a range of key improvements
- Security updates are a major focus for 3.2
- CXL has become increasingly vital in the age of AI
CXL Consortium has announced the release of its new Compute Express Link (CXL) 3.2 specifications, bringing a raft of optimized funcationalities to the technology.
In its announcement, the consortium revealed the upgraded specification will improve CXL Memory Device monitoring and management capabilities, and enhance the functionality of CXL Memory Devices for both operating systems and applications.
Security improvements are also a key talking point with the introduction of the Trusted Security Protocol (TSP).
What to expect from CXL 3.2
CXL plays a crucial role in how GPUs and CPUs interact with memory, helping to standardize cross-device communication and reduce delays. All told, this helps make systems faster and more efficient when handling large volumes of data.
With the advent of generative AI, CXL has become increasingly important given the rapid data processing requirements of applications, and this latest update will further improve upon previous specifications, particularly in terms of CXL Memory Device monitoring and management.
The new specification will include a new CXL hot page monitoring unit (CHMU) aimed specifically at streamlining memory tiering.
Similarly, the consortium unveiled compatibility with PCIe management message pass through (MMPT) alongside improvements to CXL online firmware.
Security improvements are a key focus in this latest update through TSP, the consortium noted, including new meta-bits storage features, the expansion of IDE protection, and enhanced compliance tests for interoperability.
Full backwards compatibility with previous CXL specifications was also assured by the consortium.
“We are excited to announce the release of the CXL 3.2 Specification to advance the CXL ecosystem by providing enhancements to security, compliance, and functionality of CXL Memory Devices,” said Larrie Carr, president of CXL Consortium.
“The Consortium continues to develop an open, coherent interconnect and enable an interoperable ecosystem for heterogeneous memory and computing solutions.”
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