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W159
Spread Spectrum System FTG for SMP Systems
Features
• Maximized EMI suppression using Cypress’s spread
spectrum technology (0.5% down spread)
• Seven skew-controlled copies of CPU and 16.667-MHz
synchronous APIC output
• Two copies of fixed-frequency 33-MHz outputs
• Four copies of 66-MHz fixed-frequency outputs
• Two copies of CPU/2 outputs for synchronous memory
reference
• One copy of 48-MHz USB output
• Two copies of 14.31818-MHz reference clock
• Programmable to 133- or 100-MHz operation
• Power management control pins for clock stop and shut
down
• Available in 56-pin SSOP
CPUdiv2, 3V33, APIC Output Jitter:............................250 ps
CPU, 3V33 Output Edge Rate:.................................. >1 V/ns
48-MHz, 3V66, REF Output Jitter:...............................500 ps
CPU0:6, CPUdiv2_0:1 Output Skew: ..........................175 ps
3V66, APIC0:6, 3V33 Output Skew:............................250 ps
CPU to 3V66 Output Offset: .......... 0.0 to 1.5 ns (CPU leads)
3V66 to 3V33 Output Offset: ........ 1.5 to 3.0 ns (3V66 leads)
CPU to APIC Output Offset: ............ 1 to 3.0 ns (CPU Leads)
CPU to 3V33 Output Offsets: ....... 1.5 to 4.0 ns (CPU Leads)
Logic inputs, except SEL133/100#, have 250-kΩ pull-up resis-
tors.
Table 1. Pin Selectable Frequency
SEL133/100#
1
0
CPU0:6 (MHz)
133 MHz
100 MHz
PCI
33.3 MHz
33.3 MHz
Key Specifications
Supply Voltages: ...................................... V
DDQ3
= 3.3V±5%
V
DDQ2
= 2.5V±5%
CPU Output Jitter: ...................................................... 150 ps
Block Diagram
X1
X2
Pin Configuration
2
REF_[0:1]
5
CPU_[0:4]
[1]
XTAL
OSC
6W/4W#
2
CPU_[5:6]
2
SPREAD#
÷2
CPUdiv2_[0:1]
PLL 1
4
SEL133/100#
÷2/÷1.5
3V66_[0:3]
2
PWRDWN#
÷2
3V33_[0:1]
Power
Down
Logic
FIXAPIC#
5
÷4
2
APIC_[5:6]
APIC_[0:4]
APIC2
GND
APIC1
APIC0
VDDQ2
X1
X2
VDDQ3
REF0/FIXAPIC#*
REF1/TEST#*
GND
VDDQ3
GND
48MHz
VDDQ3
3V66_0
3V66_1
VDDQ3
GND
3V66_2
3V66_3
VDDQ3
3V33_0
3V33_1
GND
6W/4W#*
VDDQ3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
APIC3
APIC4
VDDQ2
APIC5
APIC6
GND
SPREAD#*
VDDQ2
CPU0
CPU1
GND
GND
CPU2
CPU3
VDDQ2
VDDQ2
CPU4
CPU5
GND
GND
CPU6
VDDQ2
PWRDWN#*
GND
CPUdiv2_0
CPUdiv2_1
VDDQ2
SEL133/100#
Note:
1. Pins denoted by * have a 250 k
Ω
pull-up resistor. Design
should not rely solely on internal pull-up resistor to set I/O
pins HIGH.
W159
PLL2
1
48MHz
Cypress Semiconductor Corporation
Document #: 38-07163 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 25, 2001
W159
Pin Definitions
Pin Name
CPU0:6
Pin
No.
48, 47, 44, 43,
40, 39, 36
Pin
Type
O
Pin Description
CPU Clock Outputs 0 through 6:
These seven CPU clocks run at a frequency set
by SEL133/100#. Output voltage swing is set by the voltage applied to VDDQ2. For
4-way SMP systems that do not require more than 5 CPU outputs, CPU5 and CPU6
can be disabled by asserting 6W/4W# during power-up.
Synchronous Memory Reference Clock Output 0 through 1:
Reference clock
for Direct RDRAM clock generators running at 1/2 CPU clock frequency. Output
voltage swing is set by the voltage applied to VDDQ2. For systems using SDRAM,
CPUdiv2_0:1 output can be disabled by tying VDDQ2 on pin 35 to GND.
33-MHz Fixed-Frequency Output:
These are fixed-frequency outputs that can be
used to drive PCI devices.
14.318-MHz Reference Clock Output/APIC Speed Select:
During normal opera-
tions, this is a 3.3V 14.318-MHz reference output. During power-up, it is sampled
to determine the operating frequency of APIC. If the sample is a “1,” APIC will be
set at CPU/4. If it is a “0,” APIC will be fixed at 16.667 MHz.
14.318-MHz Reference Clock Output/Test Mode:
During normal operations, this
is a 3.3V 14.318-MHz reference output. The input is sampled at power-up to deter-
mine if the device should initialize for normal operations or test mode.
Synchronous I/OAPIC Clock Outputs:
APIC output frequency is determined by
FIXAPIC# strapping. For 4-way SMP systems that do not require more than 5 APIC
outputs, APIC5 and APIC6 can be disabled by asserting 4W/6W# during power up.
48-MHz Output:
Fixed 48-MHz USB output. Output voltage swing is controlled by
voltage applied to VDDQ3.
66-MHz Output 0 through 3:
Fixed 66-MHz outputs.
Frequency Selection Input:
3.3V LVTTL-compatible input that selects CPU output
frequency as shown in
Table 1.
Crystal Connection or External Reference Frequency Input:
Connect to either
a 14.318-MHz crystal or other reference signal.
Crystal Connection:
An output connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
4-way/6-way Output Select:
This input can be changed after initialization and has
an internal pull-up resistor. If left unconnected during power-up, the outputs are
configured so that all CPU and APIC outputs are active. If it is pulled down during
power-up, CPU5:6 and APIC5:6 will be disabled.
Active LOW Spread Spectrum Enable:
3.3V LVTTL-compatible input that enables
spread spectrum mode when held LOW.
Active LOW Power Down Input:
3.3V LVTTL-compatible asynchronous input that
requests the device to enter power down mode.
Ground Connection
CPUdiv2_ 0:1
32, 31
O
3V33_0:1
REF0/
FIXAPIC#*
23, 24
9
O
I/O
REF1/TEST#*
10
I/O
APIC0:6
4, 3, 1, 56, 55
53, 52
14
16, 17, 20, 21
29
6
7
26
O
48MHz
3V66_0:3
SEL133/100#
X1
X2
6W/4W#*
O
O
I
I
O
I
SPREAD#
PWRDWN#
GND
50
34
2, 11, 13, 19,
25, 28, 33, 37,
38, 45, 46, 51
8, 12, 15, 18,
22, 27
5, 30, 35, 41,
42, 49, 54
I
I
G
VDDQ3
VDDQ2
P
P
Power Connection:
Power supply for 3V33, 3V66, 48MHz, and REF output buffers,
core circuitry and PLL circuitry. Connect to 3.3V supply.
Power Connection:
Power supply for APIC and CPU, CPUdiv2 output buffers.
Connect to 2.5V supply.
All CPU, PCI, and IOAPIC clocks can be synchronously mod-
ulated for spread spectrum operations. Cypress employs pro-
prietary techniques that provide the maximum EMI reduction
while minimizing the clock skews that could reduce system
timing margins. The use of spread spectrum modulation is
controlled by an external signal input.
The W159 also includes power management control inputs. By
using these inputs, system logic can stop CPU and/or PCI
clocks or power down the entire device to conserve system
power.
Overview
The W159 is designed to provide the essential frequency
sources to work with advanced multiprocessing Intel® archi-
tecture platforms. Split voltage supply signaling provides 2.5V
and 3.3V clock frequencies operating up to 133 MHz.
From a low-cost 14.31818-MHz reference crystal oscillator,
the W159 generates 2.5V clock outputs to support CPUs, core
logic chip set, and Direct RDRAM clock generators. It also pro-
vides skew-controlled PCI and IOAPIC clocks synchronous to
CPU clock, 48-MHz Universal Serial Bus (USB) clock, and rep-
licates the 14.31818-MHz reference clock.
Document #: 38-07163 Rev. **
Page 2 of 11
W159
Spread Spectrum Generator
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in
Figure 1.
As shown in
Figure 1,
a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is
dB = 6.5 + 9*log
10
(P) + 9*log
10
(F)
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 2.
This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is –0.5% downspread.
Figure
2
details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
Spread Spectrum clocking is activated or deactivated by se-
lecting the appropriate values for the SPREAD# input pin.
Highest Peak
Spread
Spectrum
Enabled
Non-
Spread
Spectrum
Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
100%
80%
60%
40%
20%
0%
–20%
–40%
–60%
–80%
–100%
Frequency Shift
100%
Time
Figure 2. Modulation Waveform Profile
Document #: 38-07163 Rev. **
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
10%
20%
30%
40%
50%
60%
70%
80%
90%
Page 3 of 11
W159
Maximum Allowed Current
Table 2. Maximum Allowed Current
Max. 2.5V supply consumption
Max. discrete cap loads,
V
DDQ2
=2.625V
All static inputs=V
DDQ3
or V
SS
300 µA
120 mA
120 mA
Max. 3.3V supply consumption
Max. discrete cap loads,
V
DDQ3
=3.465V
All static inputs=V
DDQ3
or V
SS
500 µA
160 mA
160 mA
Condition
Power-down Mode
(PWRDWN#=0)
Full Active 100 MHz
SEL133/100#=0
Full Active 133 MHz
SEL133/100#=1
Table 3. Clock Enable Configuration
[2, 3, 4]
PWRDWN#
0
1
CPUCLK
LOW
ON
CPUdiv2
LOW
ON
APIC
LOW
ON
3V66
LOW
ON
3V33
LOW
ON
48MHz
LOW
ON
REF
LOW
ON
OSC.
OFF
ON
VCOs
OFF
ON
Table 4. Power Management State Transition
Signal
PWRDWN#
Signal State
1 (normal operation)
0 (power down)
Latency
[5]
3 ms
2 PCI clocks (max.)
Timing Diagram
PWRDWN# Timing Diagram
[6, 7, 8, 9, 10]
CPUCLK
(internal)
PCI
(internal)
PWRDWN#
CPUCLK
(external)
PCI
(external)
VCO
Crystal
Notes:
2. LOW means outputs held static LOW as per latency requirement below.
3. ON means active.
4. PWRDWN# pulled LOW, impacts all outputs including REF and 48-MHz outputs.
5. Power-up latency is when PWRDWN# goes inactive (HIGH) to when the first valid clocks are driven from the device.
6. All internal timing is referenced to the CPUCLK.
7. The internal label means inside the chip and is a reference only. This, in fact, may not be the way that the control is designed.
8. PWRDWN is an asynchronous input and metastable conditions could exist. This signal is synchronized by the W159 internally.
9. The shaded sections on the VCO and the Crystal signals indicate an active clock.
10. Diagrams shown with respect to 133 MHz. Similar operation when CPUCLK is 100 MHz.
Document #: 38-07163 Rev. **
Page 4 of 11
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