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ORCIDAndrew B. Kahng
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- affiliation: University of California, San Diego, USA
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2020 – today
- 2025
[j151]Hadi Esmaeilzadeh
, Soroush Ghodrati, Andrew B. Kahng, Sean Kinzer, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang:
Performance Analysis of CNN Inference/Training with Convolution and Non-Convolution Operations on ASIC Accelerators. ACM Trans. Design Autom. Electr. Syst. 30(1): 1-34 (2025)- 2024
- [j150]Andrew B. Kahng, Arya Mazumdar, Jodi Reeves, Yusu Wang:
The TILOS AI Institute: Integrating optimization and AI for chip design, networks, and robotics. AI Mag. 45(1): 54-60 (2024) - [j149]Suhyeong Choi, Jinwook Jung, Andrew B. Kahng, Minsoo Kim, Chul-Hong Park, Bodhisatta Pramanik, Dooseok Yoon:
PROBE3.0: A Systematic Framework for Design-Technology Pathfinding With Improved Design Enablement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1218-1231 (2024) - [j148]Ismail Bustany, Andrew B. Kahng, Ioannis Koutis, Bodhisatta Pramanik, Zhiang Wang:
K-SpecPart: Supervised Embedding Algorithms and Cut Overlay for Improved Hypergraph Partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1232-1245 (2024) - [j147]Andrew B. Kahng, Ravi Varadarajan, Zhiang Wang:
Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-Scale Complex IP Blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(5): 1552-1565 (2024) - [j146]Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar:
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route. ACM Trans. Design Autom. Electr. Syst. 29(1): 18:1-18:25 (2024) - [j145]Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Sayak Kundu, Rohan Mahapatra, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang, Ziqing Zeng:
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators. ACM Trans. Design Autom. Electr. Syst. 29(4): 1-33 (2024) - [c346]Andrew B. Kahng, Robert R. Nerem, Yusu Wang, Chien-Yi Yang:
NN-Steiner: A Mixed Neural-Algorithmic Approach for the Rectilinear Steiner Minimum Tree Problem. AAAI 2024: 13022-13030 - [c345]Andrew B. Kahng, Seokhyeong Kang, Sayak Kundu, Kyungjun Min, Seonghyeon Park, Bodhisatta Pramanik:
PPA-Relevant Clustering-Driven Placement for Large-Scale VLSI Designs. DAC 2024: 330:1-330:6 - [c344]Andrew B. Kahng, Seokhyeong Kang, Minhyuk Kweon:
Improvement of Mixed Track - Height Standard-Cell Placement. DATE 2024: 1-6 - [c343]Andrew B. Kahng, Sayak Kundu, Shreyas Thumathy:
Scalable Flip-Flop Clustering Using Divide and Conquer For Capacitated K-Means. ACM Great Lakes Symposium on VLSI 2024: 177-184 - [c342]Andrew B. Kahng, Bodhisatta Pramanik, Mingyu Woo:
A Hybrid ECO Detailed Placement Flow for Improved Reduction of Dynamic IR Drop. ACM Great Lakes Symposium on VLSI 2024: 390-396 - [c341]Andrew B. Kahng:
Panel Statement: EDA Needs at Advanced Technology Nodes. ISPD 2024: 63 - [c340]Andrew B. Kahng:
Solvers, Engines, Tools and Flows: The Next Wave for AI/ML in Physical Design. ISPD 2024: 117-124 - [c339]Joong-Won Jeon, Andrew B. Kahng, Jaehyun Kang, Jaehwan Kim, Mingyu Woo:
SLO-ECO: Single-Line-Open Aware ECO Detailed Placement and Detailed Routing Co-Optimization. ISQED 2024: 1-8 - [c338]Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Rongjian Liang, Haoxing Ren, Sachin S. Sapatnekar, Bing-Yue Wu:
OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education. VTS 2024: 1-4 - [i11]Andrew B. Kahng, Zhiang Wang:
DG-RePlAce: A Dataflow-Driven GPU-Accelerated Analytical Global Placement Framework for Machine Learning Accelerators. CoRR abs/2404.13049 (2024) - 2023
- [j144]Andrew B. Kahng:
Machine Learning for CAD/EDA: The Road Ahead. IEEE Des. Test 40(1): 8-16 (2023) - [j143]Chung-Kuan Cheng, Chester Holtz, Andrew B. Kahng, Bill Lin, Uday Mallappa:
DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs. ACM Trans. Design Autom. Electr. Syst. 28(4): 52:1-52:31 (2023) - [c337]Ismail Bustany, Grigor Gasparyan, Andrew B. Kahng, Ioannis Koutis, Bodhisatta Pramanik, Zhiang Wang:
An Open-Source Constraints-Driven General Partitioning Multi-Tool for VLSI Physical Design. ICCAD 2023: 1-9 - [c336]Jiang Hu, Andrew B. Kahng:
Invited Paper: The Inevitability of AI Infusion Into Design Closure and Signoff. ICCAD 2023: 1-7 - [c335]Jinwook Jung, Andrew B. Kahng, Sayak Kundu, Zhiang Wang, Dooseok Yoon:
Invited Paper: IEEE CEDA DATC Emerging Foundations in IC Physical Design and MLCAD Research. ICCAD 2023: 1-7 - [c334]Chung-Kuan Cheng, Andrew B. Kahng, Sayak Kundu, Yucheng Wang, Zhiang Wang:
Assessment of Reinforcement Learning for Macro Placement. ISPD 2023: 158-166 - [c333]Andrew B. Kahng, Shreyas Thumathy, Mingyu Woo:
An Effective Cost-Skew Tradeoff Heuristic for VLSI Global Routing. ISQED 2023: 1-8 - [c332]Ismail Bustany, Grigor Gasparyan, Amit Gupta, Andrew B. Kahng, Meghraj Kalase, Wuxi Li, Bodhisatta Pramanik:
The 2023 MLCAD FPGA Macro Placement Benchmark Design Suite and Contest Results. MLCAD 2023: 1-6 - [c331]Chung-Kuan Cheng, Andrew B. Kahng, Bill Lin, Yucheng Wang, Dooseok Yoon:
Gear-Ratio-Aware Standard Cell Layout Framework for DTCO Exploration. SLIP 2023: 2:1-2:10 - [i10]Chung-Kuan Cheng, Andrew B. Kahng, Sayak Kundu, Yucheng Wang, Zhiang Wang:
Assessment of Reinforcement Learning for Macro Placement. CoRR abs/2302.11014 (2023) - [i9]Andrew B. Kahng, Ravi Varadarajan, Zhiang Wang:
Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-scale Complex IP Blocks. CoRR abs/2304.11761 (2023) - [i8]Suhyeong Choi, Jinwook Jung, Andrew B. Kahng, Minsoo Kim, Chul-Hong Park, Bodhisatta Pramanik, Dooseok Yoon:
PROBE3.0: A Systematic Framework for Design-Technology Pathfinding with Improved Design Enablement. CoRR abs/2304.13215 (2023) - [i7]Ismail Bustany, Andrew B. Kahng, Ioannis Koutis, Bodhisatta Pramanik, Zhiang Wang:
K-SpecPart: A Supervised Spectral Framework for Multi-Way Hypergraph Partitioning Solution Improvement. CoRR abs/2305.06167 (2023) - [i6]Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar:
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route. CoRR abs/2305.06917 (2023) - [i5]Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Sean Kinzer, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang:
Performance Analysis of DNN Inference/Training with Convolution and non-Convolution Operations. CoRR abs/2306.16767 (2023) - [i4]Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Sayak Kundu, Rohan Mahapatra, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang, Ziqing Zeng:
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators. CoRR abs/2308.12120 (2023) - [i3]Andrew B. Kahng, Robert R. Nerem, Yusu Wang, Chien-Yi Yang:
NN-Steiner: A Mixed Neural-algorithmic Approach for the Rectilinear Steiner Minimum Tree Problem. CoRR abs/2312.10589 (2023) - 2022
- [j142]Andrew B. Kahng, Minsoo Kim, Seungwon Kim, Mingyu Woo:
RosettaStone: Connecting the Past, Present, and Future of Physical Design Research. IEEE Des. Test 39(5): 70-78 (2022) - [j141]Andrew B. Kahng, Jian Kuang, Wen-Hao Liu, Bangqi Xu:
In-Route Pin Access-Driven Placement Refinement for Improved Detailed Routing Convergence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 784-788 (2022) - [j140]Andrew B. Kahng, Lutong Wang, Bangqi Xu:
TritonRoute-WXL: The Open-Source Router With Integrated DRC Engine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 1076-1089 (2022) - [j139]Chung-Kuan Cheng, Andrew B. Kahng, Hayoung Kim, Minsoo Kim, Daeyeal Lee, Dongwon Park, Mingyu Woo:
PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1495-1508 (2022) - [c330]Andrew B. Kahng:
AI/ML, Optimization and EDA in the TILOS AI Research Institute. ACM Great Lakes Symposium on VLSI 2022: 1 - [c329]Ismail Bustany, Andrew B. Kahng, Ioannis Koutis, Bodhisatta Pramanik, Zhiang Wang:
SpecPart: A Supervised Spectral Framework for Hypergraph Partitioning Solution Improvement. ICCAD 2022: 13:1-13:9 - [c328]Andrew B. Kahng:
A Mixed Open-Source and Proprietary EDA Commons for Education and Prototyping. ICCAD 2022: 17:1-17:6 - [c327]Jinwook Jung, Andrew B. Kahng, Ravi Varadarajan, Zhiang Wang:
IEEE CEDA DATC: Expanding Research Foundations for IC Physical Design and ML-Enabled EDA. ICCAD 2022: 96:1-96:8 - [c326]Andrew B. Kahng, Ravi Varadarajan, Zhiang Wang:
RTL-MP: Toward Practical, Human-Quality Chip Planning and Macro Placement. ISPD 2022: 3-11 - [c325]Andrew B. Kahng:
Leveling Up: A Trajectory of OpenROAD, TILOS and Beyond. ISPD 2022: 73-79 - [c324]Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar:
From Global Route to Detailed Route: ML for Fast and Accurate Wire Parasitics and Timing Prediction. MLCAD 2022: 7-14 - [c323]Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Sayak Kundu, Rohan Mahapatra, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang, Ziqing Zeng:
Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML Algorithms. MLCAD 2022: 119-126 - 2021
- [j138]Andrew B. Kahng, Lutong Wang, Bangqi Xu:
TritonRoute: The Open-Source Detailed Router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(3): 547-559 (2021) - [j137]Andrew B. Kahng, Seokhyeong Kang, Seungwon Kim, Bangqi Xu:
Enhanced Power Delivery Pathfinding for Emerging 3-D Integration Technology. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 591-604 (2021) - [c322]Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Seungwon Kim, Victor N. Kravets, Yih-Lang Li, Ravi Varadarajan, Mingyu Woo:
DATC RDF-2021: Design Flow and Beyond ICCAD Special Session Paper. ICCAD 2021: 1-6 - [c321]Hadi Esmaeilzadeh, Soroush Ghodrati, Jie Gu, Shiyu Guo, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Rohan Mahapatra, Susmita Dey Manasi, Edwin Mascarenhas, Sachin S. Sapatnekar, Ravi Varadarajan, Zhiang Wang, Hanyang Xu, Brahmendra Reddy Yatham, Ziqing Zeng:
VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis. ICCAD 2021: 1-7 - [c320]Jinwook Jung, Andrew B. Kahng, Seungwon Kim, Ravi Varadarajan:
METRICS2.1 and Flow Tuning in the IEEE CEDA Robust Design Flow and OpenROAD ICCAD Special Session Paper. ICCAD 2021: 1-9 - [c319]Chung-Kuan Cheng, Andrew B. Kahng, Ilgweon Kang, Minsoo Kim, Daeyeal Lee, Bill Lin, Dongwon Park, Mingyu Woo:
CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation. ICCD 2021: 366-373 - [c318]Andrew B. Kahng:
Advancing Placement. ISPD 2021: 15-22 - 2020
- [j136]Mateus Fogaça, Andrew B. Kahng, Eder Monteiro, Ricardo Reis, Lutong Wang, Mingyu Woo:
On the superiority of modularity-based clustering for determining placement-relevant clusters. Integr. 74: 32-44 (2020) - [j135]Kwangsoo Han, Andrew B. Kahng, Jiajia Li:
Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 478-491 (2020) - [j134]Hamed Fatemi, Andrew B. Kahng, Hyein Lee, José Pineda de Gyvez:
Heuristic Methods for Fine-Grain Exploitation of FDSOI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2860-2871 (2020) - [j133]Ayse K. Coskun, Furkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma, Aditya Narayan, Vaishnav Srinivas:
Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5183-5196 (2020) - [c317]Vidya A. Chhabria, Andrew B. Kahng, Minsoo Kim, Uday Mallappa, Sachin S. Sapatnekar, Bangqi Xu:
Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques. ASP-DAC 2020: 44-49 - [c316]Andrew B. Kahng, Lutong Wang, Bangqi Xu:
The Tao of PAO: Anatomy of a Pin Access Oracle for Detailed Routing. DAC 2020: 1-6 - [c315]Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo:
DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design. ICCAD 2020: 71:1-71:6 - [c314]Andrew B. Kahng:
MLCAD Today and Tomorrow: Learning, Optimization and Scaling. MLCAD 2020: 1 - [c313]Tuck-Boon Chan, Andrew B. Kahng, Mingyu Woo:
Revisiting inherent noise floors for interconnect prediction. SLIP 2020: 10 - [c312]Hamed Fatemi, Andrew B. Kahng, Minsoo Kim, José Pineda de Gyvez:
Optimal bounded-skew steiner trees to minimize maximum k-active dynamic power. SLIP 2020: 12 - [c311]Andrew B. Kahng:
Open-Source EDA: If We Build It, Who Will Come? VLSI-SOC 2020: 1-6 - [c310]Abdelrahman Hosny, Andrew B. Kahng:
Tutorial: Open-Source EDA and Machine Learning for IC Design: A Live Update. VLSID 2020: 1-14 - [e4]Andrew B. Kahng:
SLIP '20: System-Level Interconnect - Problems and Pathfinding Workshop, San Diego, California, November 5, 2020. ACM 2020, ISBN 978-1-4503-8106-2 [contents]
2010 – 2019
- 2019
- [j132]Hamed Fatemi, Andrew B. Kahng, Hyein Lee, Jiajia Li, José Pineda de Gyvez:
Enhancing sensitivity-based power reduction for an industry IC design context. Integr. 66: 96-111 (2019) - [j131]Changho Han, Andrew B. Kahng, Lutong Wang, Bangqi Xu:
Enhanced Optimal Multi-Row Detailed Placement for Neighbor Diffusion Effect Mitigation in Sub-10 nm VLSI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9): 1703-1716 (2019) - [j130]Chung-Kuan Cheng, Andrew B. Kahng, Ilgweon Kang, Lutong Wang:
RePlAce: Advancing Solution Quality and Routability Validation in Global Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9): 1717-1730 (2019) - [c309]Yi Cao, Andrew B. Kahng, Joseph Li, Abinash Roy, Vaishnav Srinivas, Bangqi Xu:
Learning-based prediction of package power delivery network quality. ASP-DAC 2019: 160-166 - [c308]Sun ik Heo, Andrew B. Kahng, Minsoo Kim, Lutong Wang:
Diffusion break-aware leakage power optimization and detailed placement in sub-10nm VLSI. ASP-DAC 2019: 550-556 - [c307]Mateus Fogaça, Andrew B. Kahng, Ricardo Reis, Lutong Wang:
Finding placement-relevant clusters with fast modularity-based clustering. ASP-DAC 2019: 569-576 - [c306]Tutu Ajayi, Vidya A. Chhabria, Mateus Fogaça, Soheil Hashemi, Abdelrahman Hosny, Andrew B. Kahng, Minsoo Kim, Jeongsup Lee, Uday Mallappa, Marina Neseem, Geraldo Pradipta, Sherief Reda, Mehdi Saligane, Sachin S. Sapatnekar, Carl Sechen, Mohamed Shalan, William Swartz, Lutong Wang, Zhehong Wang, Mingyu Woo, Bangqi Xu:
Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project. DAC 2019: 76 - [c305]Andrew B. Kahng, Uday Mallappa, Lawrence K. Saul, Shangyuan Tong:
"Unobserved Corner" Prediction: Reducing Timing Analysis Effort for Faster Design Convergence in Advanced-Node Design. DATE 2019: 168-173 - [c304]Sun ik Heo, Andrew B. Kahng, Minsoo Kim, Lutong Wang, Chutong Yang:
Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI. DATE 2019: 830-835 - [c303]Andrew B. Kahng, Seokhyeong Kang, Seungwon Kim, Kambiz Samadi, Bangqi Xu:
Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology. DATE 2019: 842-847 - [c302]Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo:
DATC RDF-2019: Towards a Complete Academic Reference Design Flow. ICCAD 2019: 1-6 - [c301]Chia-Tung Ho, Andrew B. Kahng:
IncPIRD: Fast Learning-Based Prediction of Incremental IR Drop. ICCAD 2019: 1-8 - [c300]Andrew B. Kahng:
Looking Into the Mirror of Open Source: Invited Paper. ICCAD 2019: 1-8 - 2018
- [j129]Jiang Xu, Yuichi Nakamura, Andrew B. Kahng:
Silicon Photonics for Computing Systems. ACM J. Emerg. Technol. Comput. Syst. 14(2): 20 (2018) - [j128]Sorin Dobre, Andrew B. Kahng, Jiajia Li:
Design Implementation With Noninteger Multiple-Height Cells for Improved Design Quality in Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(4): 855-868 (2018) - [j127]Alex Kahng, Andrew B. Kahng, Hyein Lee, Jiajia Li:
PROBE: A Placement, Routing, Back-End-of-Line Measurement Utility. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1459-1472 (2018) - [c299]Andrew B. Kahng:
New directions for learning-based IC design tools and methodologies. ASP-DAC 2018: 405-410 - [c298]Kwangsoo Han, Andrew B. Kahng, Christopher Moyes, Alex Zelikovsky:
A study of optimal cost-skew tradeoff and remaining suboptimality in interconnect tree constructions. SLIP@DAC 2018: 2:1-2:8 - [c297]Andrew B. Kahng:
Reducing time and effort in IC implementation: a roadmap of challenges and solutions. DAC 2018: 36:1-36:6 - [c296]Furkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma, Saiful A. Mojumder, Tiansheng Zhang:
Leveraging thermally-aware chiplet organization in 2.5D systems to reclaim dark silicon. DATE 2018: 1441-1446 - [c295]Andrew B. Kahng, Lutong Wang, Bangqi Xu:
TritonRoute: an initial detailed router for advanced VLSI technologies. ICCAD 2018: 81 - [c294]Ayse K. Coskun, Furkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma, Vaishnav Srinivas:
A cross-layer methodology for design and optimization of networks in 2.5D systems. ICCAD 2018: 101 - [c293]Andrew B. Kahng, Uday Mallappa, Lawrence K. Saul:
Using Machine Learning to Predict Path-Based Slack from Graph-Based Timing Analysis. ICCD 2018: 603-612 - [c292]Andrew B. Kahng, Christopher Moyes, Sriram Venkatesh, Lutong Wang:
Wot the L: Analysis of Real versus Random Placed Nets, and Implications for Steiner Tree Heuristics. ISPD 2018: 2-9 - [c291]Charles J. Alpert, Wing-Kai Chow, Kwangsoo Han, Andrew B. Kahng, Zhuo Li, Derong Liu, Sriram Venkatesh:
Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees. ISPD 2018: 10-17 - [c290]Andrew B. Kahng:
Machine Learning Applications in Physical Design: Recent Results and Directions. ISPD 2018: 68-73 - [c289]Andrew B. Kahng:
Influence of Professor T. C. Hu's Works on Fundamental Approaches in Layout. ISPD 2018: 114-119 - [c288]Chung-Kuan Cheng, T. C. Hu, Andrew B. Kahng:
Theory and Algorithms of Physical Design. ISPD 2018: 130-131 - [p2]Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky:
Practical Approximations of Steiner Trees in Uniform Orientation Metrics. Handbook of Approximation Algorithms and Metaheuristics (1) 2018: 657-669 - 2017
- [j126]Wei-Ting Jonas Chan, Andrew B. Kahng, Jiajia Li:
Revisiting 3DIC benefit with multiple tiers. Integr. 58: 226-235 (2017) - [j125]Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li:
Trading Accuracy for Energy in Stochastic Circuit Design. ACM J. Emerg. Technol. Comput. Syst. 13(3): 47:1-47:30 (2017) - [j124]Rajeev Balasubramonian, Andrew B. Kahng, Naveen Muralimanohar, Ali Shafiee, Vaishnav Srinivas:
CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories. ACM Trans. Archit. Code Optim. 14(2): 14:1-14:25 (2017) - [j123]Tuck-Boon Chan, Puneet Gupta, Kwangsoo Han, Abde Ali Kagalwalla, Andrew B. Kahng:
Benchmarking of Mask Fracturing Heuristics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(1): 170-183 (2017) - [j122]José L. Abellán, Ayse K. Coskun, Anjun Gu, Warren Jin, Ajay Joshi, Andrew B. Kahng, Jonathan Klamkin, Cristian Morales, John Recchio, Vaishnav Srinivas, Tiansheng Zhang:
Adaptive Tuning of Photonic Devices in a Photonic NoC Through Dynamic Workload Allocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(5): 801-814 (2017) - [j121]Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang:
MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1075-1088 (2017) - [j120]Prabhav Agrawal, Mike Broxterman, Biswadeep Chatterjee, Patrick Cuevas, Kathy H. Hayashi, Andrew B. Kahng, Pranay K. Myana, Siddhartha Nath:
Optimal Scheduling and Allocation for IC Design Management and Cost Reduction. ACM Trans. Design Autom. Electr. Syst. 22(4): 60:1-60:30 (2017) - [j119]Farshad Firouzi, Bahar J. Farahani, Andrew B. Kahng, Jan M. Rabaey, Natasha Balac:
Guest Editorial: Alternative Computing and Machine Learning for Internet of Things. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2685-2687 (2017) - [j118]Kristof Blutman, Hamed Fatemi, Ajay Kapoor, Andrew B. Kahng, Jiajia Li, José Pineda de Gyvez:
Logic Design Partitioning for Stacked Power Domains. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3045-3056 (2017) - [c287]Kristof Blutman, Hamed Fatemi, Andrew B. Kahng, Ajay Kapoor, Jiajia Li, José Pineda de Gyvez:
Floorplan and placement methodology for improved energy reduction in stacked power-domain design. ASP-DAC 2017: 444-449 - [c286]Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang:
Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes. DAC 2017: 51:1-51:6 - [c285]Changho Han, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang, Bangqi Xu:
Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI. ICCAD 2017: 667-674 - [c284]Tuck-Boon Chan, Wei-Ting Jonas Chan, Andrew B. Kahng:
ILP-Based Identification of Redundant Logic Insertions for Opportunistic Yield Improvement during Early Process Learning. ICCD 2017: 269-272 - [c283]Wei-Ting Jonas Chan, Pei-Hsin Ho, Andrew B. Kahng, Prashant Saxena:
Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning. ISPD 2017: 15-21 - [c282]Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang:
Performance- and energy-aware optimization of BEOL interconnect stack geometry in advanced technology nodes. ISQED 2017: 104-110 - 2016
- [c281]Wei-Ting Jonas Chan, Kun Young Chung, Andrew B. Kahng, Nancy D. MacDonald, Siddhartha Nath:
Learning-based prediction of embedded memory timing failures during initial floorplan design. ASP-DAC 2016: 178-185 - [c280]Samyoung Bang, Kwangsoo Han, Andrew B. Kahng, Mulong Luo:
Delay uncertainty and signal criticality driven routing channel optimization for advanced DRAM products. ASP-DAC 2016: 697-704 - [c279]Kun Young Chung, Andrew B. Kahng, Jiajia Li:
Comprehensive optimization of scan chain timing during late-stage IC implementation. DAC 2016: 61:1-61:6 - [c278]Kwangsoo Han, Andrew B. Kahng, Jiajia Li:
Improved performance of 3DIC implementations through inherent awareness of mix-and-match die stacking. DATE 2016: 61-66 - [c277]Ayse K. Coskun, Anjun Gu, Warren Jin, Ajay Joshi, Andrew B. Kahng, Jonathan Klamkin, Yenai Ma, John Recchio, Vaishnav Srinivas, Tiansheng Zhang:
Cross-layer floorplan optimization for silicon photonic NoCs in many-core systems. DATE 2016: 1309-1314 - [c276]Andrew B. Kahng, Jiajia Li, Lutong Wang:
Improved flop tray-based design implementation for power reduction. ICCAD 2016: 20 - [c275]Andrew B. Kahng, Hyein Lee, Jiajia Li:
Measuring progress and value of IC implementation technology. ICCAD 2016: 27 - [c274]Wei-Ting Jonas Chan, Yang Du, Andrew B. Kahng, Siddhartha Nath, Kambiz Samadi:
BEOL stack-aware routability prediction from placement using data mining techniques. ICCD 2016: 41-48 - [c273]Wei-Ting Jonas Chan, Andrew B. Kahng, Jiajia Li:
Revisiting 3DIC Benefit with Multiple Tiers. SLIP 2016: 6:1-6:8 - 2015
- [j117]Andrew B. Kahng, Bill Lin, Siddhartha Nath:
ORION3.0: A Comprehensive NoC Router Estimation Tool. IEEE Embed. Syst. Lett. 7(2): 41-45 (2015) - [j116]Vivek K. De, Andrew B. Kahng, Tanay Karnik, Bao Liu, Milad Maleki, Lu Wang:
Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design. ACM J. Emerg. Technol. Comput. Syst. 12(3): 21:1-21:19 (2015) - [j115]Andrew B. Kahng, Seokhyeong Kang, Jiajia Li, José Pineda de Gyvez:
An Improved Methodology for Resilient Design Implementation. ACM Trans. Design Autom. Electr. Syst. 20(4): 66:1-66:26 (2015) - [j114]Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas:
CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1254-1267 (2015) - [j113]Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath, Bongil Park:
Optimization of Overdrive Signoff in High-Performance and Low-Power ICs. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1552-1556 (2015) - [c272]Andrew B. Kahng:
New game, new goal posts: a recent history of timing closure. DAC 2015: 4:1-4:6 - [c271]Kwangsoo Han, Jiajia Li, Andrew B. Kahng, Siddhartha Nath, Jongpil Lee:
A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction. DAC 2015: 26:1-26:6 - [c270]Wei-Ting Jonas Chan, Siddhartha Nath, Andrew B. Kahng, Yang Du, Kambiz Samadi:
3DIC benefit estimation and implementation guidance from 2DIC implementation. DAC 2015: 30:1-30:6 - [c269]Kwangsoo Han, Andrew B. Kahng, Hyein Lee:
Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router. DAC 2015: 68:1-68:6 - [c268]Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li:
Optimizing Stochastic Circuits for Accuracy-Energy Tradeoffs. ICCAD 2015: 178-185 - [c267]Andrew B. Kahng, Farinaz Koushanfar:
Evolving EDA Beyond its E-Roots: An Overview. ICCAD 2015: 247-254 - [c266]Andrew B. Kahng, Mulong Luo, Gi-Joon Nam, Siddhartha Nath, David Z. Pan, Gabriel Robins:
Toward Metrics of Design Automation Research Impact. ICCAD 2015: 263-270 - [c265]Sorin Dobre, Andrew B. Kahng, Jiajia Li:
Mixed Cell-Height Implementation for Improved Design Quality in Advanced Nodes. ICCAD 2015: 854-860 - [c264]Kwangsoo Han, Andrew B. Kahng, Hyein Lee:
Scalable Detailed Placement Legalization for Complex Sub-14nm Constraints. ICCAD 2015: 867-873 - [c263]Yao Chen, Andrew B. Kahng, Bao Liu, Wenjun Wang:
Crosstalk-aware signal probability-based dynamic statistical timing analysis. ISQED 2015: 424-429 - [c262]Andrew B. Kahng:
Modeling the future of semiconductors (and test!). ITC 2015: 8 - [c261]Samyoung Bang, Kwangsoo Han, Andrew B. Kahng, Vaishnav Srinivas:
Clock clustering and IO optimization for 3D integration. SLIP 2015: 1-8 - [c260]Marco Escalante, Andrew B. Kahng, Michael Kishinevsky, Ümit Y. Ogras, Kambiz Samadi:
Multi-product floorplan and uncore design framework for chip multiprocessors. SLIP 2015: 1-7 - [c259]Andrew B. Kahng, Mulong Luo, Siddhartha Nath:
SI for free: machine learning of interconnect coupling delay and transition effects. SLIP 2015: 1-8 - 2014
- [j112]Tuck-Boon Chan, Wei-Ting Jonas Chan, Andrew B. Kahng:
On Aging-Aware Signoff for Circuits With Adaptive Voltage Scaling. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(10): 2920-2930 (2014) - [j111]Tuck-Boon Chan, Puneet Gupta, Andrew B. Kahng, Liangzhen Lai:
Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance Monitors. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2117-2130 (2014) - [c258]Seung-Soo Han, Andrew B. Kahng, Siddhartha Nath, Ashok S. Vydyanathan:
A deep learning methodology to proliferate golden signoff timing. DATE 2014: 1-6 - [c257]Goeran Jerke, Andrew B. Kahng:
Mission profile aware IC design - A case study. DATE 2014: 1-6 - [c256]Andrew B. Kahng, Ilgweon Kang:
Co-optimization of memory BIST grouping, test scheduling, and logic placement. DATE 2014: 1-6 - [c255]Andrew B. Kahng, Hyein Lee, Jiajia Li:
Horizontal benchmark extension for improved assessment of physical CAD research. ACM Great Lakes Symposium on VLSI 2014: 27-32 - [c254]Tuck-Boon Chan, Kwangsoo Han, Andrew B. Kahng, Jae-Gon Lee, Siddhartha Nath:
OCV-aware top-level clock tree optimization. ACM Great Lakes Symposium on VLSI 2014: 33-38 - [c253]Andrew B. Kahng, Hyein Lee:
Minimum implant area-aware gate sizing and placement. ACM Great Lakes Symposium on VLSI 2014: 57-62 - [c252]Andrew B. Kahng, Seokhyeong Kang, Jiajia Li:
A new methodology for reduced cost of resilience. ACM Great Lakes Symposium on VLSI 2014: 157-162 - [c251]Tuck-Boon Chan, Puneet Gupta, Kwangsoo Han, Abde Ali Kagalwalla, Andrew B. Kahng, Emile Sahouria:
Benchmarking of mask fracturing heuristics. ICCAD 2014: 246-253 - [c250]Juan Antonio Carballo, Wei-Ting Jonas Chan, Paolo A. Gargini, Andrew B. Kahng, Siddhartha Nath:
ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap. ICCD 2014: 139-146 - [c249]Wei-Ting Jonas Chan, Andrew B. Kahng, Siddhartha Nath, Ichiro Yamamoto:
The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap. ICCD 2014: 153-160 - [c248]Tuck-Boon Chan, Sorin Dobre, Andrew B. Kahng:
Improved signoff methodology with tightened BEOL corners. ICCD 2014: 311-316 - [c247]Andrew B. Kahng, Siddhartha Nath:
Optimal reliability-constrained overdrive frequency selection in multicore systems. ISQED 2014: 300-308 - [c246]Andrew B. Kahng, Hyein Lee:
Timing margin recovery with flexible flip-flop timing model. ISQED 2014: 496-503 - [c245]Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li:
NOLO: A no-loop, predictive useful skew methodology for improved timing in IC implementation. ISQED 2014: 504-509 - [c244]Andrew B. Kahng:
Toward Holistic Modeling, Margining and Tolerance of IC Variability. ISVLSI 2014: 284-289 - [c243]Wei-Ting Jonas Chan, Andrew B. Kahng, Siddhartha Nath:
Methodology for electromigration signoff in the presence of adaptive voltage scaling. SLIP 2014: 6:1-6:7 - 2013
- [j110]Andrew B. Kahng, Seokhyeong Kang, Tajana Simunic Rosing, Richard D. Strong:
Many-Core Token-Based Adaptive Power Gating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(8): 1288-1292 (2013) - [j109]Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Enhancing the Efficiency of Energy-Constrained DVFS Designs. IEEE Trans. Very Large Scale Integr. Syst. 21(10): 1769-1782 (2013) - [c242]Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath:
Optimization of overdrive signoff. ASP-DAC 2013: 344-349 - [c241]Andrew B. Kahng, Siddhartha Nath, Tajana Rosing:
On potential design impacts of electromigration awareness. ASP-DAC 2013: 527-532 - [c240]Andrew B. Kahng:
The ITRS design technology and system drivers roadmap: process and status. DAC 2013: 34:1-34:6 - [c239]Andrew B. Kahng, Seokhyeong Kang, Hyein Lee:
Smart non-default routing for clock power reduction. DAC 2013: 91:1-91:7 - [c238]Andrew B. Kahng, Seokhyeong Kang, Bongil Park:
Active-mode leakage reduction with data-retained power gating. DATE 2013: 1209-1214 - [c237]Tuck-Boon Chan, Wei-Ting Jonas Chan, Andrew B. Kahng:
Impact of adaptive voltage scaling on aging-aware signoff. DATE 2013: 1683-1688 - [c236]Andrew B. Kahng, Bill Lin, Siddhartha Nath:
Enhanced metamodeling techniques for high-dimensional IC design estimation problems. DATE 2013: 1861-1866 - [c235]Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Igor L. Markov, Pankit Thapar:
High-performance gate sizing with a signoff timer. ICCAD 2013: 450-457 - [c234]Andrew B. Kahng, Ilgweon Kang, Siddhartha Nath:
Incremental multiple-scan chain ordering for ECO flip-flop insertion. ICCAD 2013: 705-712 - [c233]Wei-Ting Jonas Chan, Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Statistical analysis and modeling for error composition in approximate computation circuits. ICCD 2013: 47-53 - [c232]Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li:
Reliability-constrained die stacking order in 3DICs under manufacturing variability. ISQED 2013: 16-23 - [c231]Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li:
Toward quantifying the IC design value of interconnect technology improvements. SLIP 2013: 1-6 - [c230]Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Siddhartha Nath, Jyoti Wadhwani:
Learning-based approximation of interconnect delay and slew in signoff timing tools. SLIP 2013: 1-8 - [c229]Andrew B. Kahng, Bill Lin, Siddhartha Nath:
High-dimensional metamodeling for prediction of clock tree synthesis outcomes. SLIP 2013: 1-7 - 2012
- [j108]Andrew B. Kahng:
Predicting the future of information technology and society [The Road Ahead]. IEEE Des. Test Comput. 29(6): 101-102 (2012) - [j107]Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(3): 404-417 (2012) - [j106]Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi:
ORION 2.0: A Power-Area Simulator for Interconnection Networks. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 191-196 (2012) - [c228]Andrew B. Kahng, Bill Lin, Siddhartha Nath:
Explicit modeling of control and data for improved NoC router estimation. DAC 2012: 392-397 - [c227]Andrew B. Kahng, Seokhyeong Kang:
Accuracy-configurable adder for approximate arithmetic designs. DAC 2012: 820-825 - [c226]Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang, Tajana Simunic Rosing, Richard D. Strong:
MAPG: Memory access power gating. DATE 2012: 1054-1059 - [c225]Tuck-Boon Chan, Andrew B. Kahng:
Tunable sensors for process-aware voltage scaling. ICCAD 2012: 7-14 - [c224]Jin Hu, Andrew B. Kahng, Seokhyeong Kang, Myung-Chul Kim, Igor L. Markov:
Sensitivity-guided metaheuristics for accurate discrete gate sizing. ICCAD 2012: 233-239 - [c223]Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas:
CACTI-IO: CACTI with off-chip power-area-timing models. ICCAD 2012: 294-301 - [c222]Andrew B. Kahng, Seokhyeong Kang, Tajana Rosing, Richard D. Strong:
TAP: token-based adaptive power gating. ISLPED 2012: 203-208 - [c221]Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-Hung Weng:
Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph. ISPD 2012: 105-112 - [c220]Andrew B. Kahng, Seokhyeong Kang:
Construction of realistic gate sizing benchmarks with known optimal solutions. ISPD 2012: 153-160 - [c219]Tuck-Boon Chan, Andrew B. Kahng:
Improved path clustering for adaptive path-delay testing. ISQED 2012: 13-20 - [c218]Tuck-Boon Chan, Puneet Gupta, Andrew B. Kahng, Liangzhen Lai:
DDRO: A novel performance monitoring methodology based on design-dependent ring oscillators. ISQED 2012: 633-640 - 2011
- [b1]Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu:
VLSI Physical Design - From Graph Partitioning to Timing Closure. Springer 2011, ISBN 978-90-481-9590-9, pp. I-XI, 1-310 - [j105]Andrew B. Kahng:
Design for manufacturability: Then and now. IEEE Des. Test Comput. 28(1): 76-77 (2011) - [j104]Andrew B. Kahng:
Roads not taken. IEEE Des. Test Comput. 28(2): 74-75 (2011) - [j103]Andrew B. Kahng:
The Future of Signoff. IEEE Des. Test Comput. 28(3): 86-89 (2011) - [j102]Andrew B. Kahng:
Roadmapping Power. IEEE Des. Test Comput. 28(5): 104-106 (2011) - [j101]Andrew B. Kahng:
Product Futures. IEEE Des. Test Comput. 28(6): 88-89 (2011) - [j100]Andrew B. Kahng, Vijayalakshmi Srinivasan:
Big Chips. IEEE Micro 31(4): 3-5 (2011) - [c217]Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Grantham K. H. Pang, Yuanzhe Wang, Ngai Wong:
More realistic power grid verification based on hierarchical current and power constraints. ISPD 2011: 159-166 - [c216]Sung Kyu Han, Kwangok Jeong, Andrew B. Kahng, Jingwei Lu:
Stability and scalability in global routing. SLIP 2011: 1-6 - [c215]Kwangok Jeong, Andrew B. Kahng:
Toward PDN resource estimation: A law of general power density. SLIP 2011: 1-6 - [c214]Andrew B. Kahng, Vaishnav Srinivas:
Mobile system considerations for SDRAM interface trends. SLIP 2011: 1-8 - 2010
- [j99]Andrew B. Kahng:
Scaling: More than Moore's law. IEEE Des. Test Comput. 27(3): 86-87 (2010) - [j98]Andrew B. Kahng:
When is 3D 2B? IEEE Des. Test Comput. 27(4): 70-71 (2010) - [j97]Kwangok Jeong, Andrew B. Kahng, Binshan Lin, Kambiz Samadi:
Accurate Machine-Learning-Based On-Chip Router Modeling. IEEE Embed. Syst. Lett. 2(3): 62-66 (2010) - [j96]Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao:
Layout Decomposition Approaches for Double Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(6): 939-952 (2010) - [j95]Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao:
Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1070-1082 (2010) - [j94]Mohit Gupta, Kwangok Jeong, Andrew B. Kahng:
Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation for Bimodal CD Distribution in Double Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(8): 1229-1242 (2010) - [j93]Luca P. Carloni, Andrew B. Kahng, Sudhakar Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma:
Accurate Predictive Interconnect Modeling for System-Level Design. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 679-684 (2010) - [c213]Andrew B. Kahng, Bill Lin, Kambiz Samadi:
Improved on-chip router analytical power and area modeling. ASP-DAC 2010: 241-246 - [c212]Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Slack redistribution for graceful degradation under voltage overscaling. ASP-DAC 2010: 825-831 - [c211]Andrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Sunkam Ramanujam:
Trace-driven optimization of networks-on-chip configurations. DAC 2010: 437-442 - [c210]Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla, Puneet Sharma:
Eyecharts: constructive benchmarking of gate sizing heuristics. DAC 2010: 597-602 - [c209]Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Recovery-driven design: a power minimization methodology for error-tolerant processor modules. DAC 2010: 825-830 - [c208]Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Designing a processor from the ground up to allow voltage/reliability tradeoffs. HPCA 2010: 1-11 - [c207]Andrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Sunkam Ramanujam:
Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations. ICCAD 2010: 256-263 - [c206]Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang:
Toward effective utilization of timing exceptions in design optimization. ISQED 2010: 54-61 - [c205]Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topaloglu:
Assessing chip-level impact of double patterning lithography. ISQED 2010: 122-130 - [c204]Kwangok Jeong, Andrew B. Kahng:
Methodology from chaos in IC implementation. ISQED 2010: 885-892 - [c203]Chung-Kuan Cheng, Andrew B. Kahng, Kambiz Samadi, Amirali Shayan Arani:
Worst-case performance prediction under supply voltage and temperature variation. SLIP 2010: 91-96
2000 – 2009
- 2009
- [j92]Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang:
Lens aberration aware placement for timing yield. ACM Trans. Design Autom. Electr. Syst. 14(1): 16:1-16:26 (2009) - [c202]Kwangok Jeong, Andrew B. Kahng:
Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography. ASP-DAC 2009: 486-491 - [c201]Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi:
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration. DATE 2009: 423-428 - [c200]Ayse K. Coskun, Andrew B. Kahng, Tajana Simunic Rosing:
Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures. DSD 2009: 183-190 - [c199]Mohit Gupta, Kwangok Jeong, Andrew B. Kahng:
Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography. ICCAD 2009: 607-614 - [c198]Kwangok Jeong, Andrew B. Kahng, Hailong Yao:
Revisiting the linear programming framework for leakage power vs. performance optimization. ISQED 2009: 127-134 - [c197]Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topaloglu:
Is overlay error more important than interconnect variations in double patterning? SLIP 2009: 3-10 - 2008
- [j91]Andrew B. Kahng, Kambiz Samadi:
CMP Fill Synthesis: A Survey of Recent Studies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 3-19 (2008) - [j90]Andrew B. Kahng, Sudhakar Muddu, Puneet Sharma:
Defocus-Aware Leakage Estimation and Control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2): 230-240 (2008) - [j89]Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu:
Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1241-1252 (2008) - [j88]Andrew B. Kahng, Chul-Hong Park, Xu Xu:
Fast Dual-Graph-Based Hotspot Filtering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1635-1642 (2008) - [c196]Luca P. Carloni, Andrew B. Kahng, Swamy Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma:
Interconnect modeling for improved system-level design optimization. ASP-DAC 2008: 258-264 - [c195]Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester:
Investigation of diffusion rounding for post-lithography analysis. ASP-DAC 2008: 480-485 - [c194]Puneet Gupta, Andrew B. Kahng:
Bounded-lifetime integrated circuits. DAC 2008: 347-348 - [c193]Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao:
Dose map and placement co-optimization for timing yield enhancement and leakage power reduction. DAC 2008: 516-521 - [c192]Juan C. Rey, N. S. Nagaraj, Andrew B. Kahng, Fabian Klass, Rob Aitken, Cliff Hou, Luigi Capodieci, Vivek Singh:
DFM in practice: hit or hype? DAC 2008: 898-899 - [c191]Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao:
Layout decomposition for double patterning lithography. ICCAD 2008: 465-472 - [c190]Andrew B. Kahng:
How to get real mad. ISPD 2008: 69 - [c189]Kwangok Jeong, Andrew B. Kahng, Kambiz Samadi:
Quantified Impacts of Guardband Reduction on Design Process Outcomes. ISQED 2008: 790-797 - [r3]Andrew B. Kahng, Kambiz Samadi:
CMP Fill Synthesis. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [j87]Andrew B. Kahng, Ira Chayut, John M. Cohn, Toshihiro Hattori, Jeong-Taek Kong, Pierre G. Paulin, Rich Tobias:
Roundtable: Design and CAD Challenges for Leading-Edge Multimedia Designs. IEEE Des. Test Comput. 24(1): 83-93 (2007) - [j86]Charles C. Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky:
Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1): 115-126 (2007) - [j85]Andrew B. Kahng, Ion I. Mandoiu, Xu Xu, Alexander Zelikovsky:
Enhanced Design Flow and Optimizations for Multiproject Wafers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2): 301-311 (2007) - [j84]Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong:
Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 845-857 (2007) - [j83]Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester:
Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1614-1624 (2007) - [j82]Andrew B. Kahng, Bao Liu, Xu Xu:
Statistical Timing Analysis in the Presence of Signal-Integrity Effects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10): 1873-1877 (2007) - [j81]Puneet Gupta, Andrew B. Kahng, Chul-Hong Park:
Detailed Placement for Enhanced Control of Resist and Etch CDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(12): 2144-2157 (2007) - [j80]Andrew B. Kahng, Bao Liu, Qinke Wang:
Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement. IEEE Trans. Very Large Scale Integr. Syst. 15(8): 904-912 (2007) - [c188]Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh Venkataraman:
A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. ASP-DAC 2007: 24-31 - [c187]Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester:
Line-End Shortening is Not Always a Failure. DAC 2007: 270-271 - [c186]Andrew B. Kahng:
Design challenges at 65nm and beyond. DATE 2007: 1466-1467 - [c185]Andrew B. Kahng:
Key directions and a roadmap for electrical design for manufacturability. ESSCIRC 2007: 83-88 - [c184]Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu:
Exploiting STI stress for performance. ICCAD 2007: 83-90 - [c183]Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu:
Analytical thermal placement for VLSI lifetime improvement and minimum performance variation. ICCD 2007: 71-77 - [c182]Andrew B. Kahng, Swamy Muddu, Puneet Sharma:
Detailed placement for leakage reduction using systematic through-pitch variation. ISLPED 2007: 110-115 - [c181]Andrew B. Kahng, Rasit Onur Topaloglu:
A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances. ISQED 2007: 467-474 - [c180]Andrew B. Kahng, Sherief Reda, Puneet Sharma:
On-Line Adjustable Buffering for Runtime Power Reduction. ISQED 2007: 550-555 - [p1]Andrew B. Kahng, Sherief Reda, Qinke Wang:
APlace: A High Quality, Large-Scale Analytical Placer. Modern Circuit Placement 2007: 167-192 - [r2]Ion I. Mandoiu, Andrew B. Kahng, Christoph Albrecht, Alexander Zelikovsky:
Multicommodity Flow Algorithms for Buffered Global Routing. Handbook of Approximation Algorithms and Metaheuristics 2007 - [r1]Ion I. Mandoiu, Andrew B. Kahng, Alexander Zelikovsky:
Practical Approximations of Steiner Trees in Uniform Orientation Metrics. Handbook of Approximation Algorithms and Metaheuristics 2007 - [i2]Charles C. Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky:
Bright-Field AAPSM Conflict Detection and Correction. CoRR abs/0710.4661 (2007) - 2006
- [j79]Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky:
Computer-Aided Optimization of DNA Array Design and Manufacturing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(2): 305-320 (2006) - [j78]Andrew B. Kahng, Sherief Reda:
New and improved BIST diagnosis methods from combinatorial Group testing theory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 533-543 (2006) - [j77]Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng:
A Fast Hierarchical Quadratic Placement Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 678-691 (2006) - [j76]Andrew B. Kahng, Sherief Reda:
Wirelength minimization for min-cut placements via placement feedback. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1301-1312 (2006) - [j75]Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester:
Gate-length biasing for runtime-leakage control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8): 1475-1485 (2006) - [j74]Puneet Gupta, Andrew B. Kahng, Chul-Hong Park, Kambiz Samadi, Xu Xu:
Wafer Topography-Aware Optical Proximity Correction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2747-2756 (2006) - [j73]Andrew B. Kahng, Sherief Reda:
Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2806-2819 (2006) - [c179]Andrew B. Kahng:
CAD challenges for leading-edge multimedia designs. DAC 2006: 372 - [c178]Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang:
Timing-driven Steiner trees are (practically) free. DAC 2006: 389-392 - [c177]Saumil Shah, Puneet Gupta, Andrew B. Kahng:
Standard cell library optimization for leakage reduction. DAC 2006: 983-986 - [c176]Shishpal Rawat, Raul Camposano, Andrew B. Kahng, Joseph Sawicki, Mike Gianfagna, Naeem Zafar, Atul Sharan:
DFM: where's the proof of value? DAC 2006: 1061-1062 - [c175]Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang:
Lens aberration aware timing-driven placement. DATE 2006: 890-895 - [c174]Andrew B. Kahng, Bao Liu, Xu Xu:
Statistical gate delay calculation with crosstalk alignment consideration. ACM Great Lakes Symposium on VLSI 2006: 223-228 - [c173]Andrew B. Kahng, Puneet Sharma, Alexander Zelikovsky:
Fill for shallow trench isolation CMP. ICCAD 2006: 661-668 - [c172]Rasit Onur Topaloglu, Andrew B. Kahng:
Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction. ICCD 2006: 222-229 - [c171]Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan:
Efficient decoupling capacitor planning via convex programming methods. ISPD 2006: 102-107 - [c170]Andrew B. Kahng, Qinke Wang:
A faster implementation of APlace. ISPD 2006: 218-220 - [c169]Andrew B. Kahng, Bao Liu, Xu Xu:
Constructing Current-Based Gate Models Based on Existing Timing Library. ISQED 2006: 37-42 - [c168]Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan:
SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching. ISQED 2006: 638-643 - [c167]Andrew B. Kahng, Kambiz Samadi, Puneet Sharma:
Study of Floating Fill Impact on Interconnect Capacitance. ISQED 2006: 691-696 - [c166]Andrew B. Kahng, Swamy Muddu, Puneet Sharma:
Impact of Gate-Length Biasing on Threshold-Voltage Selection. ISQED 2006: 747-754 - [c165]Andrew B. Kahng, Sherief Reda:
A tale of two nets: studies of wirelength progression in physical design. SLIP 2006: 17-24 - [c164]Andrew B. Kahng, Rasit Onur Topaloglu:
Generation of design guarantees for interconnect matching. SLIP 2006: 29-34 - [c163]Andrew B. Kahng, Bao Liu, Xu Xu:
Statistical crosstalk aggressor alignment aware interconnect delay calculation. SLIP 2006: 91-97 - [c162]Puneet Gupta, Andrew B. Kahng:
Efficient Design and Analysis of Robust Power Distribution Meshes. VLSI Design 2006: 337-342 - 2005
- [j72]Andrew B. Kahng, Grant Martin:
DAC Highlights. IEEE Des. Test Comput. 22(3): 197-199 (2005) - [j71]Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao:
The Y architecture for on-chip interconnect: analysis and methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 588-599 (2005) - [j70]Andrew B. Kahng, Qinke Wang:
Implementation and extensibility of an analytic placer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5): 734-747 (2005) - [j69]Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma:
Layout-aware scan chain synthesis for improved path delay fault coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7): 1104-1114 (2005) - [j68]Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng:
Compressible area fill synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(8): 1169-1187 (2005) - [j67]Puneet Gupta, Andrew B. Kahng, Stefanus Mantik:
Routing-aware scan chain ordering. ACM Trans. Design Autom. Electr. Syst. 10(3): 546-560 (2005) - [c161]Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen:
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? ASP-DAC 2005 - [c160]Puneet Gupta, Andrew B. Kahng, Chul-Hong Park:
Detailed placement for improved depth of focus and CD control. ASP-DAC 2005: 343-348 - [c159]Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester:
Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions. DAC 2005: 365-368 - [c158]Yongseok Cheon, Pei-Hsin Ho, Andrew B. Kahng, Sherief Reda, Qinke Wang:
Power-aware placement. DAC 2005: 795-800 - [c157]Charles C. Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky:
Bright-Field AAPSM Conflict Detection and Correction. DATE 2005: 908-913 - [c156]Charles C. Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu:
Fast and efficient phase conflict detection and correction in standard-cell layouts. ICCAD 2005: 149-156 - [c155]Andrew B. Kahng, Sherief Reda:
Intrinsic shortest path length: a new, accurate a priori wirelength estimator. ICCAD 2005: 173-180 - [c154]Andrew B. Kahng, Sherief Reda, Qinke Wang:
Architecture and details of a high quality, large-scale analytical placer. ICCAD 2005: 891-898 - [c153]Andrew B. Kahng, Bao Liu, Qinke Wang:
Supply Voltage Degradation Aware Analytical Placement. ICCD 2005: 437-443 - [c152]Andrew B. Kahng, Swamy Muddu, Puneet Sharma:
Defocus-aware leakage estimation and control. ISLPED 2005: 263-268 - [c151]Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong:
Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation. ISPD 2005: 78-85 - [c150]Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia:
A semi-persistent clustering technique for VLSI circuit placement. ISPD 2005: 200-207 - [c149]Andrew B. Kahng, Sherief Reda:
Evaluation of placer suboptimality via zero-change netlist transformations. ISPD 2005: 208-215 - [c148]Andrew B. Kahng, Sherief Reda, Qinke Wang:
APlace: a general analytic placement framework. ISPD 2005: 233-235 - [c147]Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang:
Performance Driven OPC for Mask Cost Reduction. ISQED 2005: 270-275 - [c146]Puneet Gupta, Andrew B. Kahng, Puneet Sharma:
A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology. ISQED 2005: 421-426 - [e3]William H. Joyner Jr., Grant Martin, Andrew B. Kahng:
Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005. ACM 2005, ISBN 1-59593-058-2 [contents] - [i1]Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky:
Multicommodity Flow Algorithms for Buffered Global Routing. CoRR abs/cs/0508045 (2005) - 2004
- [j66]Don Edenfeld, Andrew B. Kahng, Mike Rodgers, Yervant Zorian:
2003 Technology Roadmap for Semiconductors. Computer 37(1): 47-56 (2004) - [j65]Dwight D. Hill, Andrew B. Kahng:
Guest Editors' Introduction: RTL to GDSII - From Foilware to Standard Practice. IEEE Des. Test Comput. 21(1): 9-12 (2004) - [j64]Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky:
Scalable Heuristics for Design of DNA Probe Arrays. J. Comput. Biol. 11(2/3): 429-447 (2004) - [j63]Andrew B. Kahng, Sherief Reda:
Match twice and stitch: a new TSP tour construction heuristic. Oper. Res. Lett. 32(6): 499-509 (2004) - [j62]Andrew B. Kahng, Bao Liu, Ion I. Mandoiu:
Nontree routing for reliability and yield improvement [IC layout]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 148-156 (2004) - [j61]Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong:
Effective iterative techniques for fingerprinting design IP. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(2): 208-215 (2004) - [j60]Andrew B. Kahng, Xu Xu:
Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 464-471 (2004) - [c145]Andrew B. Kahng, Sherief Reda:
Combinatorial group testing methods for the BIST diagnosis problem. ASP-DAC 2004: 113-116 - [c144]Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Makoto Mori, Qinke Wang:
Optimal planning for mesh-based power distribution. ASP-DAC 2004: 444-449 - [c143]Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang:
Toward a methodology for manufacturability-driven design rule exploration. DAC 2004: 311-316 - [c142]Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester:
Selective gate-length biasing for cost-effective runtime leakage control. DAC 2004: 327-330 - [c141]Andrew B. Kahng, Sherief Reda:
Placement feedback: a concept and method for better min-cut placements. DAC 2004: 357-362 - [c140]Dominic A. Antonelli, Danny Z. Chen, Timothy J. Dysart, Xiaobo Sharon Hu, Andrew B. Kahng, Peter M. Kogge, Richard C. Murphy, Michael T. Niemier:
Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions. DAC 2004: 363-368 - [c139]Andrew B. Kahng, Igor L. Markov, Sherief Reda:
Boosting: Min-Cut Placement with Improved Signal Delay. DATE 2004: 1098-1103 - [c138]Andrew B. Kahng, Igor L. Markov, Sherief Reda:
On legalization of row-based placements. ACM Great Lakes Symposium on VLSI 2004: 214-219 - [c137]Andrew B. Kahng, Qinke Wang:
An analytic placer for mixed-size placement and timing-driven placement. ICCAD 2004: 565-572 - [c136]Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng:
Evaluation of the new OASIS format for layout fill compression. ICECS 2004: 377-382 - [c135]Andrew B. Kahng, Qinke Wang:
Implementation and extensibility of an analytic placer. ISPD 2004: 18-25 - [c134]Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Xu Xu, Alexander Zelikovsky:
Multi-project reticle floorplanning and wafer dicing. ISPD 2004: 70-77 - [c133]Andrew B. Kahng:
Manufacturability . ISQED 2004: 8 - [c132]Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester:
Investigation of performance metrics for interconnect stack architectures. SLIP 2004: 23-29 - [c131]Puneet Gupta, Andrew B. Kahng:
Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling. VLSI Design 2004: 431-436 - [e2]Sharad Malik, Limor Fix, Andrew B. Kahng:
Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004. ACM 2004, ISBN 1-58113-828-8 [contents] - 2003
- [j59]Andrew B. Kahng:
Error Tolerance. IEEE Des. Test Comput. 20(1): 86-87 (2003) - [j58]Andrew B. Kahng:
Bringing down NRE. IEEE Des. Test Comput. 20(3): 110-111 (2003) - [j57]Andrew B. Kahng:
How much variability can designers tolerate? IEEE Des. Test Comput. 20(6): 96-97 (2003) - [j56]Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky:
Minimum buffered routing with bounded capacitive load for slew rate and reliability control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 241-253 (2003) - [j55]Christoph Albrecht, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky:
On the skew-bounded minimum-buffer routing tree problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(7): 937-945 (2003) - [j54]Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Hierarchical whitespace allocation in top-down placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11): 1550-1556 (2003) - [j53]Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester:
Improved a priori interconnect predictions and technology extrapolation in the GTX system. IEEE Trans. Very Large Scale Integr. Syst. 11(1): 3-14 (2003) - [c130]Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky:
Highly scalable algorithms for rectilinear and octilinear Steiner trees. ASP-DAC 2003: 827-833 - [c129]Puneet Gupta, Andrew B. Kahng, Stefanus Mantik:
Routing-aware scan chain ordering. ASP-DAC 2003: 857-862 - [c128]Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang:
A cost-driven lithographic correction methodology based on off-the-shelf sizing tools. DAC 2003: 16-21 - [c127]Yu Chen, Puneet Gupta, Andrew B. Kahng:
Performance-impact limited area fill synthesis. DAC 2003: 22-27 - [c126]Andrew B. Kahng, Shekhar Borkar, John M. Cohn, Antun Domic, Patrick Groeneveld, Louis Scheffer, Jean-Pierre Schoellkopf:
Nanometer design: place your bets. DAC 2003: 546-547 - [c125]Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu:
An algebraic multigrid solver for analytical placement with layout based clustering. DAC 2003: 794-799 - [c124]Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Muddu:
A Novel Metric for Interconnect Architecture Performance. DATE 2003: 10448-10455 - [c123]Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng:
Area Fill Generation With Inherent Data Volume Reduction. DATE 2003: 10868-10875 - [c122]Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao:
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. ICCAD 2003: 13-20 - [c121]Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky:
Evaluation of Placement Techniques for DNA Probe Array Layout. ICCAD 2003: 262-269 - [c120]Puneet Gupta, Andrew B. Kahng:
Manufacturing-Aware Physical Design. ICCAD 2003: 681-688 - [c119]Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma:
Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage. ICCAD 2003: 754-759 - [c118]Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky:
Design Flow Enhancements for DNA Arrays. ICCD 2003: 116- - [c117]Andrew B. Kahng, Xu Xu:
Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning. ISPD 2003: 81-86 - [c116]Andrew B. Kahng:
Research directions for coevolution of rules and routers. ISPD 2003: 122-125 - [c115]Andrew B. Kahng, Igor L. Markov:
Impact of Interoperability on CAD-IP Reuse: An Academic Viewpoint. ISQED 2003: 208-213 - [c114]Puneet Gupta, Andrew B. Kahng:
Quantifying Error in Dynamic Power Estimation of CMOS Circuits. ISQED 2003: 273-278 - [c113]Puneet Gupta, Andrew B. Kahng, Stefanus Mantik:
A Proposal for Routing-Based Timing-Driven Scan Chain Ordering. ISQED 2003: 339-343 - [c112]Andrew B. Kahng, Bao Liu:
Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization. ISVLSI 2003: 183-188 - [c111]Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky:
Engineering a scalable placement heuristic for DNA probe arrays. RECOMB 2003: 148-156 - [c110]Andrew B. Kahng, Xu Xu:
Accurate pseudo-constructive wirelength and congestion estimation. SLIP 2003: 61-68 - [c109]Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang:
Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing. SLIP 2003: 71-76 - 2002
- [j52]Alan Allan, Don Edenfeld, William H. Joyner Jr., Andrew B. Kahng, Mike Rodgers, Yervant Zorian:
2001 Technology Roadmap for Semiconductors. Computer 35(1): 42-53 (2002) - [j51]Andrew B. Kahng:
Variability. IEEE Des. Test Comput. 19(3): 120, 116 (2002) - [j50]Andrew B. Kahng:
The Road Ahead: The significance of packaging. IEEE Des. Test Comput. 19(6): 104-105 (2002) - [j49]Joshua N. Cooper, Robert B. Ellis, Andrew B. Kahng:
Asymmetric Binary Covering Codes. J. Comb. Theory A 100(2): 232-249 (2002) - [j48]Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky:
Provably good global buffering by generalized multiterminalmulticommodity flow approximation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(3): 263-274 (2002) - [j47]Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky:
Area fill synthesis for uniform layout density. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10): 1132-1147 (2002) - [j46]Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt:
Toward better wireload models in the presence of obstacles. IEEE Trans. Very Large Scale Integr. Syst. 10(2): 177-189 (2002) - [c108]Andrew B. Kahng, Ronald Collett, Patrick Groeneveld, Lavi Lev, Nancy Nettleton, Paul K. Rodman, Lambert van den Hoven:
Tools or users: which is the bigger bottleneck? DAC 2002: 76-77 - [c107]Andrew B. Kahng, Bao Liu, Ion I. Mandoiu:
Non-tree routing for reliability and yield improvement. ICCAD 2002: 260-266 - [c106]C. Bandela, Yu Chen, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky:
Auctions with Buyer Preferences. Information Systems: The e-Business Challenge 2002: 223-238 - [c105]Andrew B. Kahng:
A roadmap and vision for physical design. ISPD 2002: 112-117 - [c104]Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky:
Closing the smoothness and uniformity gap in area fill synthesis. ISPD 2002: 137-142 - [c103]Andrew B. Kahng, Stefanus Mantik, Igor L. Markov:
Min-max placement for large-scale timing optimization. ISPD 2002: 143-148 - [c102]Andrew B. Kahng, Gary Smith:
A New Design Cost Model for the 2001 ITRS (invited). ISQED 2002: 190-193 - [c101]Andrew B. Kahng, Stefanus Mantik:
Measurement of Inherent Noise in EDA Tools. ISQED 2002: 206-212 - [c100]Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky:
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing. ASP-DAC/VLSI Design 2002: 580- - [c99]Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky:
Border Length Minimization in DNA Array Design. WABI 2002: 435-448 - 2001
- [j45]William H. Joyner Jr., Andrew B. Kahng:
Guest Editor's Introduction: Roadmaps and Visions for Design and Test. IEEE Des. Test Comput. 18(6): 4-5 (2001) - [j44]Randal E. Bryant, Kwang-Ting Cheng, Andrew B. Kahng, Kurt Keutzer, Wojciech Maly, A. Richard Newton, Lawrence T. Pileggi, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli:
Limitations and challenges of computer-aided design technology for CMOS VLSI. Proc. IEEE 89(3): 341-365 (2001) - [j43]Andrew B. Kahng, Stefanus Mantik, Dirk Stroobandt:
Toward accurate models of achievable routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5): 648-659 (2001) - [j42]Andrew B. Kahng, John C. Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe:
Constraint-based watermarking techniques for design IP protection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(10): 1236-1252 (2001) - [c98]Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky:
Provably good global buffering by multi-terminal multicommodity flow approximation. ASP-DAC 2001: 120-125 - [c97]Andrew B. Kahng, Shailesh Vaya, Alexander Zelikovsky:
New graph bipartizations for double-exposure, bright field alternating phase-shift mask layout. ASP-DAC 2001: 133-138 - [c96]Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky:
Hierarchical dummy fill for process uniformity. ASP-DAC 2001: 139-144 - [c95]Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori:
Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. ASP-DAC 2001: 267-268 - [c94]Andrew B. Kahng:
Design technology productivity in the DSM era (invited talk). ASP-DAC 2001: 443-448 - [c93]Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt:
Toward better wireload models in the presence of obstacles. ASP-DAC 2001: 527-532 - [c92]Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang:
Panel: Is Nanometer Design Under Control? DAC 2001: 591-592 - [c91]Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky:
Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control. ICCAD 2001: 408- - [c90]Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia:
Buffered Steiner trees for difficult instances. ISPD 2001: 4-9 - [c89]Andrew B. Kahng, Ronald Collett, Ton. H. van de Kraats:
Design Metrics to Achieve Design Quality. ISQED 2001: 9 - [c88]Andrew B. Kahng, Stefanus Mantik:
A System for Automatic Recording and Prediction of Design Quality Metrics. ISQED 2001: 81-86 - [c87]Andrew B. Kahng, Sudhakar Muddu, Niranjan Pol, Devendra Vidhani:
Noise Model for Multiple Segmented Coupled RC Interconnects. ISQED 2001: 145-150 - [c86]Kenneth D. Boese, Andrew B. Kahng, Stefanus Mantik:
On the relevance of wire load models. SLIP 2001: 91-98 - [c85]Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu:
Interconnect implications of growth-based structural models for VLSI circuits. SLIP 2001: 99-106 - [c84]Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky:
Practical Approximation Algorithms for Separable Packing Linear Programs. WADS 2001: 325-337 - 2000
- [j41]Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning. ACM J. Exp. Algorithmics 5: 5 (2000) - [j40]Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Huijuan Wang, Alexander Zelikovsky:
Optimal phase conflict removal for layout of dark field alternatingphase shifting masks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2): 175-187 (2000) - [j39]Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Hypergraph partitioning with fixed vertices [VLSI CAD]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2): 267-272 (2000) - [j38]Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Optimal partitioners and end-case placers for standard-cell layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11): 1304-1313 (2000) - [j37]Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Iterative Partitioning with Varying Node Weights. VLSI Design 11(3): 249-258 (2000) - [c83]Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky:
Monte-Carlo algorithms for layout density control. ASP-DAC 2000: 523-528 - [c82]Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Improved algorithms for hypergraph bipartitioning. ASP-DAC 2000: 661-666 - [c81]Andrew B. Kahng, Sudhakar Muddu, Egino Sarto:
On switch factor based analysis of coupled RC interconnects. DAC 2000: 79-84 - [c80]Jennifer Smith, Tom Quan, Andrew B. Kahng:
EDA meets.COM (panel session): how E-services will change the EDA business model. DAC 2000: 253 - [c79]Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Can recursive bisection alone produce routable placements? DAC 2000: 477-482 - [c78]Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky:
Practical iterated fill synthesis for CMP uniformity. DAC 2000: 671-674 - [c77]Andrew E. Caldwell, Yu Cao, Andrew B. Kahng, Farinaz Koushanfar, Hua Lu, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester:
GTX: the MARCO GSRC technology extrapolation system. DAC 2000: 693-698 - [c76]Stephen Fenstermaker, David George, Andrew B. Kahng, Stefanus Mantik, Bart Thielges:
METRICS: a system architecture for design process optimization. DAC 2000: 705-710 - [c75]Andrew B. Kahng, Stefanus Mantik:
On Mismatches between Incremental Optimizers and Instance Perturbations in Physical Design Tools. ICCAD 2000: 17-21 - [c74]Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester:
Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. ICCAD 2000: 56-61 - [c73]Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky:
Provably Good Global Buffering Using an Available Buffer Block Plan. ICCAD 2000: 104-109 - [c72]Andrew B. Kahng, Stefanus Mantik, Dirk Stroobandt:
Requirements for models of achievable routing. ISPD 2000: 4-11 - [c71]Andrew B. Kahng:
Classical floorplanning harmful? ISPD 2000: 207-213 - [c70]Marcelo O. Johann, Andrew E. Caldwell, Ricardo Augusto da Luz Reis, Andrew B. Kahng:
Admissibility Proofs for the LCS* Algorithm. IBERAMIA-SBIA 2000: 236-244 - [c69]Andrew B. Kahng, Dirk Stroobandt:
Wiring layer assignments with consistent stage delays. SLIP 2000: 115-122
1990 – 1999
- 1999
- [j36]Charles J. Alpert, Andrew B. Kahng, So-Zen Yao:
Spectral Partitioning with Multiple Eigenvectors. Discret. Appl. Math. 90(1-3): 3-26 (1999) - [j35]Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky:
Filling algorithms and analyses for layout density control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4): 445-462 (1999) - [j34]Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky:
On wirelength estimations for row-based placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1265-1278 (1999) - [j33]Andrew B. Kahng, Sudhakar Muddu, Egino Sarto:
Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron ICs. VLSI Design 10(1): 21-34 (1999) - [j32]Charles J. Alpert, Andrew E. Caldwell, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, M. S. Moroz:
Analytical Engines are Unnecessary in Top-down Partitioning-based Placement. VLSI Design 10(1): 99-116 (1999) - [c68]Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning. ALENEX 1999: 177-193 - [c67]Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky:
New Multilevel and Hierarchical Algorithms for Layout Density Control. ASP-DAC 1999: 221-224 - [c66]Ross Baldick, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov:
Function Smoothing with Applications to VLSI Layout. ASP-DAC 1999: 225- - [c65]Andrew B. Kahng, Paul Tucker, Alexander Zelikovsky:
Optimization of Linear Placements for Wirelength Minimization with Free Sites. ASP-DAC 1999: 241-244 - [c64]Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov:
Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting. DAC 1999: 349-354 - [c63]Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Hypergraph Partitioning with Fixed Vertices. DAC 1999: 355-359 - [c62]Andrew B. Kahng, Y. C. Pati, Warren Grobman, Robert Pack, Lance A. Glasser:
Subwavelength Lithography: How Will It Affect Your Design Flow? (Panel). DAC 1999: 798 - [c61]Andrew B. Kahng, Y. C. Pati:
Subwavelength Lithography and Its Potential Impact on Design and EDA. DAC 1999: 799-804 - [c60]Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong:
Effective Iterative Techniques for Fingerprinting Design IP. DAC 1999: 843-848 - [c59]Yu Chen, Andrew B. Kahng, Gang Qu, Alexander Zelikovsky:
The associative-skew clock routing problem. ICCAD 1999: 168-172 - [c58]Andrew B. Kahng, Darko Kirovski, Stefanus Mantik, Miodrag Potkonjak, Jennifer L. Wong:
Copy detection for intellectual property protection of VLSI designs. ICCAD 1999: 600-605 - [c57]Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Optimal partitioners and end-case placers for standard-cell layout. ISPD 1999: 90-96 - [c56]Andrew B. Kahng, Y. C. Pati:
Subwavelength optical lithography: challenges and impact on physical design. ISPD 1999: 112-119 - [c55]Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Huijuan Wang, Alexander Zelikovsky:
Optimal phase conflict removal for layout of dark field alternating phase shifting masks. ISPD 1999: 121-126 - [c54]Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Partitioning with terminals: a "new" problem and new benchmarks. ISPD 1999: 151-157 - [c53]Andrew B. Kahng:
Mini-Tutorial: IC Layout and Manufacturability: Critical Links and Design Flow Implications. VLSI Design 1999: 100-105 - [c52]Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky:
New and Exact Filling Algorithms for Layout Density Control. VLSI Design 1999: 106-110 - [c51]Andrew B. Kahng, Sudhakar Muddu, Egino Sarto:
Interconnect Optimization Strategies for High-Performance VLSI Designs. VLSI Design 1999: 464-469 - [c50]Andrew B. Kahng, Sudhakar Muddu:
Improved Effective Capacitance Computations for Use in Logic and Layout Optimization. VLSI Design 1999: 578-583 - [c49]Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Alexander Zelikovsky:
The T-join Problem in Sparse Graphs: Applications to Phase Assignment Problem in VLSI Mask Layout. WADS 1999: 25-36 - 1998
- [j31]Andrew B. Kahng, Gabriel Robins, Elizabeth A. Walkup:
How to test a tree. Networks 32(3): 189-197 (1998) - [j30]Andrew B. Kahng, Majid Sarrafzadeh:
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(1): 1-2 (1998) - [j29]Charles J. Alpert, Tony F. Chan, Andrew B. Kahng, Igor L. Markov, Pep Mulet:
Faster minimization of linear wirelength for global placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(1): 3-13 (1998) - [j28]Jason Cong, Andrew B. Kahng, Kwok-Shing Leung:
Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(1): 24-39 (1998) - [j27]Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng:
Multilevel circuit partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8): 655-667 (1998) - [j26]Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao:
Bounded-skew clock and Steiner routing. ACM Trans. Design Autom. Electr. Syst. 3(3): 341-388 (1998) - [c48]Andrew B. Kahng, John C. Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe:
Watermarking Techniques for Intellectual Property Protection. DAC 1998: 776-781 - [c47]Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe:
Robust IP Watermarking Methodologies for Physical Design. DAC 1998: 782-787 - [c46]Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma:
Interconnect Tuning Strategies for High-Performance Ics. DATE 1998: 471-478 - [c45]Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky:
On wirelength estimations for row-based placement. ISPD 1998: 4-11 - [c44]Andrew B. Kahng, Gabriel Robins, Anish Singh, Huijuan Wang, Alexander Zelikovsky:
Filling and slotting: analysis and algorithms. ISPD 1998: 95-102 - [c43]Andrew B. Kahng, Sudhakar Muddu:
New efficient algorithms for computing effective capacitance. ISPD 1998: 147-151 - [c42]Andrew B. Kahng:
Futures for partitioning in physical design (tutorial). ISPD 1998: 190-193 - 1997
- [j25]Y. Uny Cao, Alex S. Fukunaga, Andrew B. Kahng:
Cooperative Mobile Robotics: Antecedents and Directions. Auton. Robots 4(1): 7-27 (1997) - [j24]Inki Hong, Andrew B. Kahng, Byung Ro Moon:
Improved Large-Step Markov Chain Variants for the Symmetric TSP. J. Heuristics 3(1): 63-81 (1997) - [j23]Lars W. Hagen, Andrew B. Kahng:
Combining problem reduction and adaptive multistart: a new technique for superior iterative partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(7): 709-717 (1997) - [j22]Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng:
On implementation choices for iterative improvement partitioning algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10): 1199-1205 (1997) - [j21]Andrew B. Kahng, Sudhakar Muddu:
An analytical delay model for RLC interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(12): 1507-1514 (1997) - [j20]Andrew B. Kahng, Sudhakar Muddu:
Analysis of RC interconnections under ramp input. ACM Trans. Design Autom. Electr. Syst. 2(2): 168-192 (1997) - [j19]Andrew B. Kahng, Chung-Wen Albert Tsao:
Practical Bounded-Skew Clock Routing. J. VLSI Signal Process. 16(2-3): 199-215 (1997) - [c41]Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng:
Multilevel Circuit Partitioning. DAC 1997: 530-533 - [c40]Andrew B. Kahng, Chung-Wen Albert Tsao:
More Practical Bounded-Skew Clock Routing. DAC 1997: 594-599 - [c39]Jason Cong, Lei He, Andrew B. Kahng, David Noice, Nagesh Shirali, Steve H.-C. Yen:
Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology. DAC 1997: 627-632 - [c38]Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, Pep Mulet, Kenneth Yan:
Faster minimization of linear wirelength for global placement. ISPD 1997: 4-11 - [c37]Dennis J.-H. Huang, Andrew B. Kahng:
Partitioning-based standard-cell global placement with an exact objective. ISPD 1997: 18-25 - [c36]Jason Cong, Andrew B. Kahng, Kwok-Shing Leung:
Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. ISPD 1997: 88-95 - [e1]Andrew B. Kahng, Majid Sarrafzadeh:
Proceedings of the 1997 International Symposium on Physical Design, ISPD 1997, Napa Valley, California, USA, April 14-16, 1997. ACM 1997, ISBN 0-89791-927-0 [contents] - 1996
- [j18]Andrew B. Kahng, Chung-Wen Albert Tsao:
Planar-DME: a single-layer zero-skew clock tree router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(1): 8-19 (1996) - [j17]Charles J. Alpert, Andrew B. Kahng:
A general framework for vertex orderings with applications to circuit clustering. IEEE Trans. Very Large Scale Integr. Syst. 4(2): 240-246 (1996) - [c35]Andrew B. Kahng, Sudhakar Muddu:
Analysis of RC Interconnections Under Ramp Input. DAC 1996: 533-538 - [c34]Andrew B. Kahng, Kei Masuko, Sudhakar Muddu:
Analytical delay models for VLSI interconnects under ramp input. ICCAD 1996: 30-36 - 1995
- [j16]T. C. Hu, Andrew B. Kahng, Chung-Wen Albert Tsao:
Old Bachelor Acceptance: A New Class of Non-Monotone Threshold Accepting Methods. INFORMS J. Comput. 7(4): 417-425 (1995) - [j15]Charles J. Alpert, Andrew B. Kahng:
Recent directions in netlist partitioning: a survey. Integr. 19(1-2): 1-81 (1995) - [j14]Charles J. Alpert, T. C. Hu, Dennis J.-H. Huang, Andrew B. Kahng, David R. Karger:
Prim-Dijkstra tradeoffs for improved performance-driven routing tree design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(7): 890-896 (1995) - [j13]Charles J. Alpert, Andrew B. Kahng:
Multiway partitioning via geometric embeddings, orderings, and dynamic programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(11): 1342-1358 (1995) - [j12]Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins:
Near-optimal critical sink routing tree constructions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1417-1436 (1995) - [c33]Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng:
Quantified Suboptimality of VLSI Layout Heuristics. DAC 1995: 216-221 - [c32]Dennis J.-H. Huang, Andrew B. Kahng, Chung-Wen Albert Tsao:
On the Bounded-Skew Clock and Steiner Routing Problems. DAC 1995: 508-513 - [c31]Dennis J.-H. Huang, Andrew B. Kahng:
When clusters meet partitions: new density-based methods for circuit decomposition. ED&TC 1995: 60-64 - [c30]Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng:
On implementation choices for iterative improvement partitioning algorithms. EURO-DAC 1995: 144-149 - [c29]Dennis J.-H. Huang, Andrew B. Kahng:
Multi-way System Partitioning into a Single Type or Multiple Types of FPGAs. FPGA 1995: 140-145 - [c28]Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao:
Bounded-skew clock and Steiner routing under Elmore delay. ICCAD 1995: 66-71 - [c27]Andrew B. Kahng, Byung Ro Moon:
Toward More Powerful Recombinations. ICGA 1995: 96-103 - [c26]Y. Uny Cao, Alex S. Fukunaga, Andrew B. Kahng, F. Meng:
Cooperative mobile robotics: antecedents and directions. IROS (1) 1995: 226-234 - 1994
- [j11]Kenneth D. Boese, Andrew B. Kahng, Sudhakar Muddu:
A new adaptive multi-start technique for combinatorial global optimizations. Oper. Res. Lett. 16(2): 101-113 (1994) - [j10]Lars W. Hagen, Andrew B. Kahng, Fadi J. Kurdahi, Champaka Ramachandran:
On the intrinsic Rent parameter and spectra-based partitioning methodologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(1): 27-37 (1994) - [j9]Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh:
On the Minimum Density Interconnection Tree Problem. VLSI Design 2(2): 157-169 (1994) - [c25]Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins:
Rectilinear Steiner Trees with Minimum Elmore Delay. DAC 1994: 381-386 - [c24]Andrew B. Kahng, Sudhakar Muddu:
Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model. DAC 1994: 563-569 - [c23]Charles J. Alpert, Andrew B. Kahng:
Multi-Way Partitioning Via Spacefilling curves and Dynamic Programming. DAC 1994: 652-657 - [c22]Sudhakar Muddu, Andrew B. Kahng:
Optimal equivalent circuits for interconnect delay calculations using moments. EURO-DAC 1994: 164-169 - [c21]Chung-Wen Albert Tsao, Andrew B. Kahng:
Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay. EURO-DAC 1994: 440-445 - [c20]Charles J. Alpert, Andrew B. Kahng:
A general framework for vertex orderings, with applications to netlist clustering. ICCAD 1994: 63-67 - [c19]Andrew B. Kahng, Chung-Wen Albert Tsao:
Low-cost single-layer clock trees with exact zero Elmore delay skew. ICCAD 1994: 213-218 - 1993
- [j8]Jason Cong, Andrew B. Kahng, Gabriel Robins:
Matching-based methods for high-performance clock routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(8): 1157-1169 (1993) - [j7]T. C. Hu, Andrew B. Kahng, Gabriel Robins:
Optimal robust path planning in general environments. IEEE Trans. Robotics Autom. 9(6): 775-784 (1993) - [c18]Kenneth D. Boese, Andrew B. Kahng, Gabriel Robins:
High-Performance Routing Trees With Identified Critical Sinks. DAC 1993: 182-187 - [c17]Charles J. Alpert, Andrew B. Kahng:
Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning. DAC 1993: 743-748 - [c16]Kenneth D. Boese, Andrew B. Kahng, Chung-Wen Albert Tsao:
Best-so-far vs. where-you-are: New perspectives on simulated annealing for CAD. EURO-DAC 1993: 78-83 - [c15]Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins:
Fidelity and Near-Optimality of Elmore-Based Routing Constructions. ICCD 1993: 81-84 - [c14]Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh:
Minimum Density Interconneciton Trees. ISCAS 1993: 1865-1868 - [c13]Charles J. Alpert, T. C. Hu, Jen-Hsin Huang, Andrew B. Kahng:
A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing. ISCAS 1993: 1869-1872 - [c12]Kenneth D. Boese, Andrew B. Kahng:
Simulated annealing of neural networks: The 'cooling' strategy reconsidered. ISCAS 1993: 2572-2575 - 1992
- [j6]Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar:
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. IEEE Des. Test Comput. 9(3): 7-20 (1992) - [j5]Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, Chak-Kuen Wong:
Provably good performance-driven global routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(6): 739-752 (1992) - [j4]Andrew B. Kahng, Gabriel Robins:
A new class of iterative Steiner tree heuristics with good performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(7): 893-902 (1992) - [j3]Lars W. Hagen, Andrew B. Kahng:
New spectral methods for ratio cut partitioning and clustering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(9): 1074-1085 (1992) - [j2]Andrew B. Kahng, Gabriel Robins:
On the performance bounds for a class of rectilinear Steiner tree heuristics in arbitrary dimension. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(11): 1462-1465 (1992) - [c11]Jason Cong, Lars W. Hagen, Andrew B. Kahng:
Net Partitions Yield Better Module Partitions. DAC 1992: 47-52 - [c10]Lars W. Hagen, Fadi J. Kurdahi, Champaka Ramachandran, Andrew B. Kahng:
On the intrinsic rent parameter and spectra-based partitioning methodologies. EURO-DAC 1992: 202-208 - [c9]Lars W. Hagen, Andrew B. Kahng:
A new approach to effective circuit clustering. ICCAD 1992: 422-427 - [c8]Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen:
An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. ICCD 1992: 154-158 - 1991
- [j1]Andrew B. Kahng, Gabriel Robins:
Optimal algorithms for extracting spatial regularity in images. Pattern Recognit. Lett. 12(12): 757-764 (1991) - [c7]Andrew B. Kahng, Jason Cong, Gabriel Robins:
High-Performance Clock Routing Based on Recursive Geometric Aatching. DAC 1991: 322-327 - [c6]Lars W. Hagen, Andrew B. Kahng:
Fast Spectral Methods for Ratio Cut Partitioning and Clustering. ICCAD 1991: 10-13 - [c5]Andrew B. Kahng:
An Effective Analog Approach to Steiner Routing. ICCD 1991: 166-169 - [c4]Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, C. K. Wong:
Performance-Driven Global Routing for Cell Based ICs. ICCD 1991: 170-173 - 1990
- [c3]T. C. Hu, Andrew B. Kahng:
Every Tree is Graceful (But Some are More Graceful than Others). Applied Geometry And Discrete Mathematics 1990: 355-358 - [c2]Andrew B. Kahng, Gabriel Robins:
A New Class of Steiner Trees Heuristics with Good Performance: The Iterated 1-Steiner-Approach. ICCAD 1990: 428-431
1980 – 1989
- 1989
- [c1]Andrew B. Kahng:
Fast Hypergraph Partition. DAC 1989: 762-766
Coauthor Index
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