A great achievement!
Professor of Electronic Engineering, Royal Academy of Engineering / Microchip Senior Research Chair in High-Temperature Electronics
Shoutout to my group Victor Marot, Dr. MUKESH KUMAR KULSRESHATH, Elliott Worsey, Qi Tang, Roshan Weerasekera, Qijia Tang, Manu Bala Krishnan and collaborators, Harold Chong, Frank Niklaus, Simon J. Bleiker, YUE FAN, Yingying Li 李蓥荥 for the excellent work that led to a journal paper and four conference papers accepted / presented in January, on topics ranging from nanomechanical relay technology to efficient digital circuits to lightweight ML models for edge computing. Much of this work was done or carried on from the EU funded i-EDGE project and ZeroAMP project. Energy Consumption in Micro and Nanoelectromechanical Relays published in IEEE Transactions on Electron Devices (see https://lnkd.in/ejvYhrwp) provides an in-depth analysis of the energy consumption of micro and nanomechanical digital switches including the first reported energy measurements and a new model for the dynamic energy consumption. In Reconfigurable Non-Volatile 4-Way Routing Switch With Zero Standby Power presented at IEEE MEMS in Taiwan in January, we demonstrate a routing circuit made up of four non-volatile nanoelectromechanical (NEM) relays that can achieve 15 different connection patterns between four bidirectional ports. In Nanomechanical Relay-based Switchblock For FPGA Interconnect to be presented at ISCAS 2025 in London in May, we show how the efficiency of this switch block can be leveraged to create island-style FPGA switchblocks with more flexibility than is possible with CMOS. In Nanoelectromechanical Binary Comparator for Edge-Computing Applications to be presented at DATE 2025 in Lyon, we propose a new class of binary comparator circuit using 4-terminal nanoelectromechanical (NEM) relays that use just 6 devices compared to 9 transistors in CMOS implementations. In DT2HDL: A Binary Decision Tree to HDL Generation tool to be presented at ISQED in San Francisco in April, we propose a framework for automatically generating Hardware Description Language (HDL) code for binary decision trees, which are suitable for lightweight classification implementations at the edge.