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0.5-V input digital LDO with 98.7% current efficiency and ...
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由 Y Okuma 著作2010被引用 368 次 — The developed digital LDO in 65nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-μA quiescent current at ...
0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7 ...
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2024年10月22日 — The developed digital LDO in 65 nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-mu A quiescent current.
[PDF] 0.5-V input digital LDO with 98.7% current efficiency ...
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The developed digital LDO in 65nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage are the lowest values in the published LDO's.
0.5-V Input Digital LDO with 98.7% Current Efficiency and ...
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由 Y Okuma 著作被引用 368 次 — The developed digital LDO in 65nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-µA quiescent current at ...
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0.5-V input digital LDO with 98.7% current efficiency and ...
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2024年10月22日 — The developed digital LDO in 65nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-μA ...
0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7 ...
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The developed digital LDO in 65nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-µA quiescent current at ...
0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7 ...
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The developed digital LDO in 65 nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage are the lowest values in the published LDO's, ...
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A fully integrated fast transient response digital low-dropout ...
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由 M Xin 著作2023 — 0.5-V input digital LDO with 98.7% current efficiency and 2.7-μA quiescent current in 65-nm CMOS. K.Z. Ahmed. A variation-adaptive integrated computational ...
Digital LDO modelling techniques for performance ...
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由 S Leitner 著作2018被引用 1 次 — 3. Okama Y., Ishida K., Ryu Y., et al: '0.5-V input digital LDO with 98.7% current efficiency and 2.7-μA quiescent current in 65 nm CMOS'. Proc. Custom ...
A 0.38 V near/sub-VT digitally controlled low-dropout ...
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Okuma Y., Ishida K., Ryu Y., et al: '0.5-V input digital LDO with 98.7% current efficiency and 2.7-μA quiescent current in 65 nm CMOS'. Proc. IEEE Custom ...
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