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A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ...
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Abstract: An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring ...
A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power ...
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由 K Yoshioka 著作2013被引用 1 次 — Abstract—An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring ...
A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power ...
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An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator ...
A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ...
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A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ...
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An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator ...
吉岡 健太郎 (Kentaro Yoshioka) - A 0.35-0.8V 8b 0.5-35MS/s 2bit ...
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An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator ...
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ASP-DAC 2025
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由 K Yoshioka 著作被引用 1 次 — A 0.35-0.8V 8b 0.5-35MS/s 2bit/step. Extremely-Low Power SAR ADC. Kentaro Yoshioka, Akira Shikata,. Ryota Sekimoto, Tadahiro Kuroda and Hiroki Ishikuro.
Ryota Sekimoto
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An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. ... A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power ...
Design Contest｜ASP DAC Award Archive
ASP-DAC 2025
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A 0.35-0.8V 8b 0.5-35MS/s 2bit/step Extremely-low Power SAR ADC. A 0.35-0.8V 8b 0.5-35MS/s 2bit/step Extremely-. Keio Univ., Japan; Kentaro Yoshioka, Akira ...
Details of a Researcher - Kuroda, Tadahiro
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0.5V Image Processor with 563 GOPS/W SIMD and 32bit CPU Using High Voltage ... A 0.35-0.8V 8b 0.5-35MS/s 2bit/step Extremely-low Power SAR ADC,. KURODA ...