[en] A new circuit for identifying the amount of input channels is described. Its applications, operation principle, circuit structure and circuit design are introduced as well. The instrument is provided with functions of multi-input, pulse signal logical summation and input channels identification. This instrument is very useful in nuclear physics experiments to monitor and identify the occurrence of the multi-coincidental or inter-related events

[en] This paper describes the circuits of a 16 channel CL repeater

[en] Several practical circuits that make it possible to tie a random signal to a signal of regular sequence are described. The circuits employ logical elements of AND-NOT type and triggers of D and J-K type

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[en] UCF is a unified network protocol and FPGA firmware for high speed serial interfaces employed in Data Acquisition systems. It provides up to 64 different communication channels via a single serial link. One channel is reserved for timing and trigger information whereas the other channels can be used for slow control interfaces and data transmission. All channels are bidirectional and share network bandwidth according to assigned priority. The timing channel distributes messages with fixed and deterministic latency in one direction. From this point of view the protocol implementation is asymmetrical. The precision of the timing channel is defined by the jitter of the recovered clock and is typically in the order of 10-20 ps RMS. The timing channel has highest priority and a slow control interface should use the second highest priority channel in order to avoid long delays due to high traffic on other channels. The framework supports point-to-point connections and star-like 1:n topologies but only for optical networks with passive splitter. It always employs one of the connection parties as a master and the others as slaves. The star-like topology can be used for front-ends with low data rates or pure time distribution systems. In this case the master broadcasts information according to assigned priority whereas the slaves communicate in a time sharing manner to the master.

[en] A device for fast triggering based on parallel memory look up tables is described. It is designed to be used with three tracking detectors (hodoscopes) consisting of 32 elements. The device can analyze up to three coordinates in each hodoscope during the time no more than 160 ns. An integrated circuit K500PY415 as the memory element is used. The first part of the paper describes electronics and software for its testing. The second part describes the design of the hodoscopes, service software and look up table contents calculations and experimental results. 3 refs.; 8 figs.; 1 tab

[en] Precision synchronization of high brightness facility is obtained and a delay triggering control signal is produced with wide range (1 ns∼999 μs) high precision (1ns) adjustment and multi-pass out-put (20 passes) through the use of high performance fast-ECL circuit, standard frequency counting method and high precision linear saw tooth wave voltage generator

[en] Two novel neural chips SAND (Simple Applicable Neural Device) and SIOP (Serial Input - Operating Parallel) are described. Both are highly usable for hardware triggers in particle physics. The chips are optimized for a high input data rate at a very low cost basis. The performance of a single SAND chip is 200 MOPS due to four parallel 16 bit multipliers and 40 bit adders working in one clock cycle. The chip is able to implement feedforward neural networks, Kohonen feature maps and radial basis function networks. Four chips will be implemented on a PCI-board for simulation and on a VUE board for trigger and on- and off-line analysis. For small sized feedforward neural networks the bit-serial neuro-chip SIOP may lead to even smaller latencies because each synaptic connection is implemented by its own bit serial multiplier and adder

No abstract available