[en] The Tile Calorimeter (TileCal) is the hadronic calorimeter covering the central region of the ATLAS experiment at LHC. The TileCal readout consists of about 10000 channels. The bulk of its upgrade will occur for the High Luminosity LHC phase (Phase-II) where the peak luminosity will increase 5 times compared to the design luminosity (10"3"4 cm"−"2s"−"1) but with maintained energy (i.e. 7+7 TeV). An additional increase of the average luminosity with a factor of 2 can be achieved by luminosity levelling. This upgrade is expected to happen around 2024. The TileCal upgrade aims at replacing the majority of the on- and off- detector electronics to the extent that all calorimeter signals will be digitized and sent to the off-detector electronics in the counting room. To achieve the required reliability, redundancy has been introduced at different levels. Three different options are presently being investigated for the front-end electronic upgrade. Extensive test beam studies will determine which option will be selected. 10 Gbps optical links are used to read out all digitized data to the counting room while 5 Gbps down-links are used for synchronization, configuration and detector control. For the off-detector electronics a pre-processor (sROD) is being developed, which takes care of the initial trigger processing while temporarily storing the main data flow in pipeline and derandomizer memories. One demonstrator prototype module with the new calorimeter module electronics, but still compatible with the present system, is planned to be inserted in ATLAS this year

[en] This work presents an overview of the on-detector and off-detector electronics for the Phase II Upgrade of the ATLAS Tile Calorimeter at the LHC scheduled around 2022. Three options are being studied for the implementation of the new front-end readout: an improved version of the 3-in-1 card, a new version of the QIE chip and a dedicated ASIC called FATALIC. Moreover, the MainBoard will manage incoming signals from the FEBs and the DaughterBoard will send the digitized data to the off-detector electronics where the sROD will perform processing tasks on them. This work summarizes the status of the project

[en] This work summarizes the status of the on-detector and off-detector electronics developments for the Phase 2 Upgrade of the ATLAS Tile Calorimeter at the LHC scheduled around 2022. A demonstrator prototype for a slice of the calorimeter including most of the new electronics is planned to be installed in ATLAS in the middle of 2014 during the first Long Shutdown. For the on-detector readout, three different front-end boards (FEB) alternatives are being studied: a new version of the 3-in-1 card, the QIE chip and a dedicated ASIC called FATALIC. The Main Board will provide communication and control to the FEBs and the Daughter Board will transmit the digitized data to the off-detector electronics in the counting room, where the super Read-Out Driver (sROD) will perform processing tasks on them and will be the interface to the trigger levels 0, 1 and 2. (authors)

[en] The Tile Calorimeter PreProcessor demonstrator is a high performance double AMC board based on FPGA resources and QSFP modules. This board has been designed in the framework of the ATLAS Tile Calorimeter Demonstrator project for the Phase II Upgrade as the first stage of the back-end electronics. The TilePPr demonstrator has been conceived to receive and process the data coming from the front-end electronics of the TileCal Demonstrator module, as well as to configure it. Moreover, the TilePPr demonstrator handles the communication with the Detector Control System to monitor and control the front-end electronics. The TilePPr demonstrator represents 1/8 of the final TilePPr that will be designed and installed into the detector for the ATLAS Phase II Upgrade

[en] The analog signals generated in the read-out electronics of particle detectors are shaped prior to the digitization in order to improve the signal to noise ratio (SNR). The real amplitude of the analog signal is then obtained using digital filters, which provides information about the energy deposited in the detector. The classical digital filters have a good performance in ideal situations with Gaussian electronic noise and no pulse shape distortion. However, high-energy particle colliders, such as the Large Hadron Collider (LHC) at CERN, can produce multiple simultaneous events, which produce signal pileup. The performance of classical digital filters deteriorates in these conditions since the signal pulse shape gets distorted. In addition, this type of experiments produces a high rate of collisions, which requires high throughput data acquisitions systems. In order to cope with these harsh requirements, new read-out electronics systems are based on high-performance FPGAs, which permit the utilization of more advanced real-time signal reconstruction algorithms. In this paper, a deep learning method is proposed for real-time signal reconstruction in high pileup particle detectors. The performance of the new method has been studied using simulated data and the results are compared with a classical FIR filter method. In particular, the signals and FIR filter used in the ATLAS Tile Calorimeter are used as benchmark. The implementation, resources usage and performance of the proposed Neural Network algorithm in FPGA are also presented.

[en] This paper describes the upgraded portable test bench for the Tile Calorimeter of the ATLAS experiment at CERN. The previous version of the portable test bench was extensively used for certification and qualification of the front-end electronics during the commissioning phase as well as during the short maintenance periods of 2010 and 2011. The new version described here is designed to be an easily upgradable version of the 10-year-old system, able to evaluate the new technologies planned for the ATLAS upgrade as well as provide new functionalities to the present system. It will be used in the consolidation of electronics campaign during the long shutdown of the LHC in 2013-14 and during future maintenance periods. The system, based on a global re-design with state-of-the-art devices, is based on a back-end electronics crate instrumented with commercial and custom modules and a front-end GUI that is executed on an external portable computer and communicates with the controller in the crate through an Ethernet connection. (authors)

[en] This paper describes a new portable test bench for the TileCal sub-detector of the ATLAS experiment at CERN. The system is used for the certification and quality checks of the front-end electronics drawers. It is designed to be an easily upgradable version of the current 10-year-old system, able to evaluate the new technologies planned for the upgrade as well as provide new functionality to the present system. It will be used during the long shutdown of the LHC in 2013-14 and during future maintenance periods.