[en] The international DEPFET collaboration is developing a silicon pixel vertex detector (PXD), based on monolithic arrays of DEPFET transistors, for the future physics experiment Belle-II at the SuperKEKB particle accelerator in Japan. The matrix elements are read out in a 'rolling shutter mode', i.e. rows are selected consecutively and all columns are read out in each cycle of < 100 ns. One of the major parts in the front-end electronics chain is the DEPFET Current Digitizer ASIC (DCDB). It is now in a close-to-final state. The chip provides 256 channels of analog-to-digital converters with a resolution of six to eight bits. Each converter features an individual dynamic offset correction circuit as well as programmable gain and bandwidth. Several operation modes using single sampling or double correlated sampling are possible. A large synthesized digital block is used for decoding and derandomization of the conversion results. The data is put out on eight 8-bit links, operating at a speed of 400 MHz. Additionally, a JTAG compatible interface is implemented for configuration and debugging purpose. Significant effort was made to reduce the power consumption of the DCDB, since both, voltage drop on the internal power buses and heat sources in the Belle-II experiment are a concern. The chip was realized on a 3.2mm x 5mm die using the UMC 180nm CMOS technology in a multi-project wafer run, provided by EuroPractice. An extra redistribution metal layer with bump bond pads is used, allowing for flipping the chip onto the final all-silicon DEPFET sensor module. Several tests have been performed in order to prove the chip's operation and its quality in terms of noise. The results are presented.

[en] Particle pixel detectors in standard high-voltage CMOS technology are a new detector family that allows implementation of low-cost radiation-tolerant detectors with good time resolution. In order to test the concept we have implemented three detector variants. The first variant uses simple four-transistor pixel electronics that allows the rolling-shutter readout. The second variant implements complex CMOS pixel electronics with particle hit detection on pixel level and binary readout. The third variant uses the readout based on the capacitive chip-to-chip signal transmission. In this paper we will present the recent experimental results.

[en] Hybrid pixel-detectors for the detection of elementary particles without bump-interconnections will be presented. The signals, generated in the sensor chip, are transmitted using capacitive coupling to the readout chip. In order to ease the capacitive signal transmission, an active pixel sensor has been used. The sensor chip is implemented in a standard CMOS high-voltage technology where lowly doped n-well in p-substrate diodes are used as pixel-sensors. CMOS in-pixel preamplifiers are implemented inside the n-wells. Experimental results obtained with two different hybrid detector prototypes will be presented.

[en] The high-voltage (HV-) CMOS pixel sensors offer several good properties: a fast charge collection by drift, the possibility to implement relatively complex CMOS in-pixel electronics and the compatibility with commercial processes. The sensor element is a deep n-well diode in a p-type substrate. The n-well contains CMOS pixel electronics. The main charge collection mechanism is drift in a shallow, high field region, which leads to a fast charge collection and a high radiation tolerance. We are currently evaluating the use of the high-voltage detectors implemented in 180 nm HV-CMOS technology for the high-luminosity ATLAS upgrade. Our approach is replacing the existing pixel and strip sensors with the CMOS sensors while keeping the presently used readout ASICs. By intelligence we mean the ability of the sensor to recognize a particle hit and generate the address information. In this way we could benefit from the advantages of the HV sensor technology such as lower cost, lower mass, lower operating voltage, smaller pitch, smaller clusters at high incidence angles. Additionally we expect to achieve a radiation hardness necessary for ATLAS upgrade. In order to test the concept, we have designed two HV-CMOS prototypes that can be readout in two ways: using pixel and strip readout chips. In the case of the pixel readout, the connection between HV-CMOS sensor and the readout ASIC can be established capacitively

[en] The paper is based on the data of the 2009 DEPFET beam test at CERN SPS. The beam test used beams of pions and electrons with energies between 40 and 120 GeV, and the sensors tested were prototypes with thickness of 450μm and pixel pitch between 20 and 32μm. Intrinsic resolutions of the detectors are calculated by disentangling the contributions of measurement errors and multiple scattering in tracking residuals. Properties of the intrinsic resolution estimates and factors that influence them are discussed. For the DEPFET detectors in the beam test, the calculation yields intrinsic resolutions of ∼1μm, with a typical accuracy of 0.1μm. Bias scan, angle scan, and energy scan are used as example studies to show that the intrinsic resolutions are a useful tool in studies of detector properties. With sufficiently precise telescopes, detailed resolution maps can be constructed and used to study and optimize detector performance.

[en] Large arrays of depleted field effect transistor (DEPFET) detector elements are one possible technology for the vertex detector of the planned International Linear Collider. The main challenges are the production of large (10cm²) devices with an average thickness of around 100μm (silicon) and their fast column parallel readout. This paper describes in some detail how a DEPFET based sensor module could be built and presents the design of the latest generation of 'Switcher' steering chips

[en] In a DEPleted Field Effect Transistor (DEPFET) sensor a MOSFET is integrated on a sidewards depleted p-on-n silicon detector, thereby combining the advantages of a fully depleted silicon sensor with in-pixel amplification. A 450 μm thick DEPFET was tested in a testbeam. The S/N was found to be larger than 110. The position resolution is better than 5 μm. At a seed cut of 7σ, the efficiency and purity are both close to 100%. In the readout chip a zero-suppression capability is implemented. The functionality was demonstrated using a radio-active source. The predicted impact parameter resolution of a 50 μm thick DEPFET vertex detector, is much better than required for the International Linear Collider (ILC)