[en] In this article, β-Ga₂O₃ film was deposited on the p-Si (100) substrate using pulsed laser deposition (PLD) technique for rapidly emerging Ga₂O₃-based Schottky barrier diodes (SBDs). Although X-ray diffraction (XRD) result reveals a polycrystalline trending film, a smooth and uniform as-grown surface has been characterized by atomic force microscope (AFM) and field-emission scanning electron microscope (FESEM). Further, we have investigated metal–semiconductor (M–S) contact behavior of the fully vertical SBDs with the four different metals such as aluminum (Al), silver (Ag), gold (Au), and platinum (Pt) on Ga₂O₃ after forming ohmic contacts on the backside of the Si substrate. The barrier heights of all four metals are typically in the range of 0.51–0.69 eV and 0.72–1.41 eV as obtained from the current–voltage (I–V) and capacitance–voltage (C–V) characteristics, respectively. The carrier concentration is ~ 10¹⁶ cm⁻³ as calculated using C–V characteristics. The power device indices, namely breakdown voltage (V_BR) of 19, 26, 90, and 99 V and the on-state resistance (R_ON) values ~ 19.82, 149.19, 7.45 and 156.25 Ω cm² are also obtained for the Al/Ga₂O₃, Ag/Ga₂O₃, Au/Ga₂O₃, and Pt/Ga₂O₃ diodes, respectively. The Baliga Figure of Merits (V²_BR/R_ON) for the Au/Ga₂O₃ diode is found out to be the highest (90.73 W cm⁻²). As the SBDs are fabricated on n-Ga₂O₃/p-Si heterojunction, it is expected to have two back-to-back diodes in the device structure. However, non-existence of back-to-back diodes has been confirmed by temperature dependence I–V characteristics due to possible Poole–Frenkel (P–F) tunneling at the Ga₂O₃/Si heterojunction.

[en] Metal–insulator–semiconductor (MIS)-based Pt/La₂O₃/SiO_XN_Y/p-Si/Pt structures are fabricated using ultrathin silicon oxynitride (SiO_XN_Y ~ 4 nm) interfacial layer underneath of lanthanum (III) oxide (La₂O₃ ~ 7.8 nm) with Pt as gate electrode for CMOS applications. Capacitance–voltage (C–V) characteristics of Pt/La₂O₃/SiO_XN_Y/p-Si/Pt at 500 kHz showed a positive gate bias threshold voltage (V_th) shift of ~ 0.43 V (~ 43.8%) and flat-band (V_fb) shift of ~ 1.24 V (~ 42.3%) as compared to Pt/La₂O₃/p-Si/Pt MIS structures, attributing to the reduction in effective positive oxide charges at La₂O₃/SiO_XN_Y/Si gate stack. Likewise, conductance–voltage (G–V) characteristics show ~ 0.56 (~ 44.4%) reduction in FWHM for Pt/La₂O₃/SiO_XN_Y/p-Si/Pt as compared to Pt/La₂O₃/p-Si/Pt MIS structures revealing the reduction in interface states at La₂O₃/SiO_XN_Y/Si interface. There is a considerable reduction of effective oxide charge concentration (N_eff) ~ 3.99 × 10¹⁰ cm⁻² by (~ 15.2%) and ~ 56.8% lower gate leakage current density ~ 4.47 × 10⁻⁷ A/cm² ( J –V) at − 1 V for SiO_XN_Y based MIS structures w.r.t its counterpart. Capacitance–time (C–t) characteristics, constant voltage stress (CVS) and temperature measurements for C–V and J –V demonstrate the considerable retention ~ 12 years, electrical improvement and reliability of MIS structures. The depth profile analysis X-ray photoelectron spectroscopy (XPS) for SiO_XN_Y/Si gate stack clearly reveals that less nitrogen concentration in bulk than SiO_XN_Y/Si interface. Atomic force microscopy (AFM) micrographs of La₂O₃/Si and SiO_XN_Y/Si showed the significantly lesser r.m.s roughness of ~ 1.11 ± 0.39 nm and ~ 0.97 ± 0.11 nm, respectively. Thus, the ultrathin SiO_XN_Y interfacial layer underneath of La₂O₃ demonstrates a significantly improved electrical performance and prelude the gate stack strong potential for reliable CMOS logic devices and integrated circuits.

[en] The effect of constant negative voltage stress on charge trapping and interface states of Al/HfO₂/SiO_xN_y/Si structures are investigated. The reduction in the capacitance of C-t characteristics and a significant shift in C-V curves towards negative voltage axis reveal that the charge trapping/detrapping occurs at the Si/SiO_xN_y/HfO₂ interface and HfO₂ bulk. However, there is a relative increase in gate leakage current as a function of the voltage stress and time, owing to the trap-assisted tunnelling. It is suggested that these traps are probably Hf-OH neutral centers, originating from the breaking of bridging Si-OH and Si-NH bonds by mobile H⁺ protons. This has potential application in non-volatile CMOS memory devices.

[en] The synthesis of cadmium sulfide (CdS) nanowires using a simple chemical reaction (ion exchange) method through the pores in an alumina template is reported. The chemical reaction takes place inside the pores and the reaction yield is deposited in the pores. The morphological, structural and optical characterization of CdS nanowires is also reported. The Raman spectrum shows that CdS nanowries have good crystalline nature. The value of the optical bandgap observed is 2.7 eV for CdS nanowires. Room temperature photoluminescence measurements exhibit an emission peak at about 507 nm.

[en] Present study develops a facile, low-temperature and cost-effective route for the synthesis of nitrogen-doped reduced graphene oxide (N-rGO). The synthesized N-rGO was characterized using X-ray diffraction (XRD), micro-Raman and Fourier transform infrared (FTIR) spectroscopies. An electrochemical sensor using N-rGO-modified glassy carbon electrode (GCE) was fabricated for the determination of dopamine (DA), a neurotransmitter. Because the electrochemical determination and quantification of DA play a significant role in medical diagnosis, such as making soft material-based hydro- gel for wound healing. Cyclic voltammetry (CV), amperometry, differential pulse voltammetry (DPV) and electrochemical impedance spectroscopy (EIS)-based standard techniques were used to evaluate and establish the optimum electrochemical sensing performance, detection limit, steadiness and reliability of N-rGO/GCE sensing system to the DA detection. The DPV measurements resemble a wide linear range from 100 to 3000 μ M and demonstrated a limit of detection (LOD) of 57 nM. It is evidently proved that N-rGO/GCE has great potential to be a preferable electrochemical sensing system for DA detection. K. (author)

[en] Emerging information technology and data deluge foster the unprecedented demands of higher chip density, clocking speed, data storage and lower power dissipation for on-chip non-volatile memories (NVMs). Here, two types of metal-insulator-metal (MIM) based NVM structures were fabricated and demonstrated involving controlled functionalization of molybdenum disulfide (MoS₂) and graphene oxide (GO) nanocomposite as a resistive switching layer. The first type of device constitutes Aluminum (Al) top and bottom electrode resulting in the Al/MoS₂-GO/Al structure. While the second type of device uses Al top electrode and Indium Tin Oxide (ITO) bottom electrode resulting in Al/MoS₂-GO/ITO. The current-voltage (I–V) characteristics for fabricated Al/MoS₂-GO/Al and Al/MoS₂-GO/ITO MIM structures exhibited considerable I_ON/I_OFF ratio of ∼10² (SET and RESET state at 0.5 V and −0.4 V) and ∼10¹ (SET and RESET state at 0.3 V and −1 V), respectively. The I–V characteristics for Al/MoS₂-GO/Al MIM structure showed low voltage switching, substantial memory retention ∼10⁴ s and endurance for up to 25 cycles. The low voltage and controlled switching operation for Al/MoS₂-GO/Al MIM structures may be attributed to the presence of a large number of oxygen vacancies, defects in MoS₂-GO, promoting enhanced charge hopping via interfacial oxide at MoS₂-GO/Al interface as compared to MoS₂-GO/ITO. (paper)

[en] The effect of plasma immersion ion implantation (PIII) treatment on silicon surfaces was investigated by micro-Raman and atomic force microscopy (AFM) technique. The surface damage was given by the implantation of carbon, nitrogen, oxygen and argon ions using an inductively coupled plasma (ICP) source at low pressure. AFM studies show that surface topography of the PIII treated silicon wafers depend on the physical and chemical nature of the implanted species. Micro-Raman spectra indicate that the significant reduction of intensity of Raman peak after PIII treatment. Plasma immersion ion implantation is a non-line-of-sight ion implantation method, which allows 3D treatment of materials. Therefore, PIII based surface modification and plasma immersion ion deposition (PIID) coatings are applied in a wide range of situations.

[en] The development of new photoresist materials for multi-lithography applications is crucial but a challenging task for semiconductor industries. During the last few decades, given the need for new resists to meet the requirements of semiconductor industries, several research groups have developed different resist materials for specific lithography applications. In this context, we have successfully synthesized a new molecular non-chemically amplified resist (n-CAR) (C3) based on the functionalization of aromatic hydroxyl core (4,4′-(9H-fluorene-9,9-diyl)diphenol) with radiation sensitive sulfonium triflates for various lithography applications. While, micron scale features have been developed using i-line (365 nm) and DUVL (254 nm) exposure tools, electron beam studies on C3 thin films enabled us to pattern 20 nm line features with L/3S (line/space) characteristics on the silicon substrate. The sensitivity and contrast were calculated from the contrast curve analysis as 280 µC cm⁻² and 0.025 respectively. Being an important parameter for any newly developed resists, the line edge roughness (LER) of 30 nm (L/5S) features were calculated, using SUMMIT metrology package, to be 3.66  ±  0.3 nm and found to be within the acceptable range. AFM analysis further confirmed 20 nm line width with smooth pattern wall. No deformation of patterned features was observed during AFM analysis which indicated good adhesion property between patterned resists and silicon substrates. (paper)

[en] Highly UV sensitive sub-5 nm Sn nanoparticles-Polyaniline (Sn (NPs)-PANI) composite material has been formulated by chemical polymerisation. A thin film of the composite is deposited on Micro-Interdigitated Electrode (µ-IDEs) array for photodetector application. Considerably, higher optical density (10–12), w.r.t carbon of Sn (NPs) in Sn (NPs)-PANI/Al-IDE/Glass structures exhibit the exceedingly enhanced sensitivity towards UV illumination. There is substantial large contrast ratio of ∼ 2290 at − 1 V, significantly large responsivity ∼ 3.05 A/W, detectivity of ~ 2.26E + 13 Jones and reasonable rise/fall time of ∼ 0.7/1.7 s observed for Sn (NPs)-PANI/Al-IDE/Glass devices. Surface morphology, phase analysis, and elemental composition of Sn–PANI systems have been investigated by X-ray diffraction and Energy Dispersive X-ray analysis (EDX), respectively. Transmission electron microscopy (TEM) analysis confirms the size of the Sn (NPs) and blend with Polyaniline. The significantly enhanced sensitivity of ~ 228514.3 for λ ~ 254 nm establishes the clear potential of the fabricated structure for UV-C detector application.

[en] Electroless based Ni-Co-P alloy thin films were deposited using sodium hypophosphite as a reducing agent and sodium citrate as a complexing agent in an alkaline plating bath. The effect of solution pH and temperature on the plating rate was examined. The decrease in activation energy (81.35 − 73.54 kJ mole"−"1) for the Ni-Co-P thin films deposited on corning glass was observed with the increase in pH (8.5–9.38) of the plating bath. There is a significant decrease in sheet resistance of alloy thin films as the post deposition annealing temperature approaches 400 °C. The presence of nickel as well as nickel phosphide peaks and transition from metastable Ni_1_2P_5, Ni_8P_5 and Ni_5P_2 phases into thermodynamically stable NiP, NiP_2, Ni_3P phases after annealing at 600 °C was observed in XRD spectra, indicating the crystallization of the thin films. Surface topography analysis shows the variation of grain size in the range 20–40 nm. (paper)