[en] In the past few years, ASIC (Application Specific Integrated Circuit) design has become important at Fermilab. The purpose of this paper is to present an overview of the in-house ASIC design activity which has taken place. This design effort has added much value to the high energy physics program and physics capability at Fermilab. The two approaches to ASIC development being pursued at Fermilab are examined by looking at some of the types of projects where ASICs are being used or contemplated. To help estimate the cost of future designs, a cost comparison is given to show the relative development and production expenses for these two ASIC approaches. 5 refs., 14 figs., 7 tabs

[en] Pixelated amorphous silicon arrays used for detecting X-rays have a number of special requirements for the readout electronics. Because the pixel detector is a high density array, custom integrated circuits are very desirable for reading out the column signals and addressing the rows of pixels to be read out. In practice, separate chips are used for readout and addressing. This paper discusses a custom integrated circuit for processing the analog column signals. The chip has 32 channels of low noise integrators followed by sample and hold circuits which perform a correlated double sample. The chip has several programmable features including gain, bandwidth, and readout configuration

[en] In the late 1980's, several versions of a full custom chip called the SVX were built and tested. The chip was designed to be a second generation silicon strip readout chip incorporating new features such as data sparsification for silicon strip detectors. The SVX designed by Stuart Kleinfelder and others at LBL contained 128 channels of electronics and proved to be very popular. Initially the chip was fabricated in 3.0 micron process and later transferred to a 1.2 micron radiation hard process. Based on the success of the first SVX (referred herein as SVXI), a need arose for a third generation device. This new 128 channel device called the SVXII was developed by a collaboration of engineers at Fermilab and Lawrence Berkeley Laboratory. The SVXII, designed in a 1.2 micron process, contains many new features including analog storage and digitization of the analog information. In addition to the new features, the SXVII is intended to operate with interaction times approximately 25 times faster than the original SVX, have the same or better noise characteristics, and have a minimal increase in power. The SVXII is an engineering challenge. This report is a first detailed attempt to introduce the SVXIII to the user. Knowledge of the original SVX and its operation would be helpful and can be obtained from references 1--3

[en] Three dimensional integrated circuits are well suited to improving circuit bandwidth and increasing effective circuit density. Recent advances in industry have made 3D integrated circuits an option for HEP. The 3D technology is discussed in this paper and several examples are shown. Design of a 3D demonstrator chip for the ILC is presented

[en] Work was begun in 1990 on the development of an advanced readout chip (ARC) for silicon strip detectors. Features of the proposed device include compatibility with close bunch spacing and double sided detectors, and on chip analog storage, digitization, and data sparsification. Chip have been designed to check all of these concepts, fabricated in the VTI 2 micron process, and tested. The circuit configurations and test results are presented in this paper

[en] In 1997 an order was placed with Honeywell for 265 four-inch SVX3 wafers. After the initial delivery, the processing line at Honeywell was switched to 6-inch wafers. It was quickly apparent that there were serious problems on the 6-inch wafers which were not seen on the 4-inch wafers. Wafers from one of the 6-inch lots generally have a high yield and do not exhibit the center-of-the-wafer via problem. It is not known if bad vias will recover or good vias go bad with time, temperature and radiation.

[en] This paper reports on a SOI detector with drift field induced by the flow of majority carriers. It is proposed as an alternative method of detector biasing compared to standard depletion. N-drift rings in n-substrate are used at the front side of the detector to provide charge collecting field in depth as well as to improve the lateral charge collection. The concept was verified on a 2.5 x 2.5 mm² large detector array with 20 (micro)m and 40 (micro)m pixel pitch fabricated in August 2009 using the OKI semiconductor process. First results, obtained with a radioactive source to demonstrate spatial resolution and spectroscopic performance of the detector for the two different pixel sizes will be shown and compared to results obtained with a standard depletion scheme. Two different diode designs, one using a standard p-implantation and one surrounded by an additional BPW implant will be compared as well.

[en] This paper reports on the current status of the development of International Linear Collider vertex detector pixel readout chips based on multi-tier vertically integrated electronics. Initial testing results of the VIP2a prototype are presented. The chip is the second embodiment of the prototype data-pushed readout concept developed at Fermilab. The device was fabricated in the MIT-LL 0.15 (micro)m fully depleted SOI process. The prototype is a three-tier design, featuring 30 x 30 (micro)m² pixels, laid out in an array of 48 x 48 pixels.

[en] Work was begun in 1990 on the development of an advanced readout chip (ARC) for silicon strip detectors. Features of the proposed device include compatibility with close bunch spacing and double sided detectors, and on chip analog storage, digitization, and data sparsification. Chips have been designed to check all of these concepts, fabricated in the VTI 2 micron process, and tested. The circuit configurations and test results are presented in this paper

[en] A description is given of the R and D program underway at Fermilab to develop a pixel readout ASIC appropriate for use at the Tevatron collider. Results are presented from tests performed on the first prototype pixel readout chip designed at Fermilab, and a new readout architecture is described. (author)