Yeong-Jar Chang - researchr alias

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Viewing Publication 1 - 15 from 15

2021

Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D ICJai-Ming Lin, Wei-Yi Chang, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu. tvlsi, 29(9):1652-1664, 2021. [doi]

Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force ModulationJai-Ming Lin, Tai-Ting Chen, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu. tvlsi, 29(5):985-997, 2021. [doi]

2019

Intelligent Policy Selection for GPU Warp SchedulerLih-Yih Chiou, Tsung-Han Yang, Jian-Tang Syu, Che-Pin Chang, Yeong-Jar Chang. aicas 2019: 302-303 [doi]

2018

Fast Steady-State Thermal AnalysisLih-Yih Chiou, Chun-Hao Chang, Liang-Ying Lu, Wei-Hsuan Yang, Yeong-Jar Chang, Juin-Ming Lu. isocc 2018: 15-16 [doi]

A fast thermal-aware fixed-outline floorplanning methodology based on analytical modelsJai-Ming Lin, Tai-Ting Chen, Yen-Fu Chang, Wei-Yi Chang, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu. iccad 2018: [doi]

2010

Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay BuffersYu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang. tcad, 29(12):1921-1930, 2010. [doi]

2009

On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS ProcessMing-Dou Ker, Po-Yen Chiu, Fu-Yi Tsai, Yeong-Jar Chang. iscas 2009: 2281-2284 [doi]

Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designsYu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang. iccad 2009: 535-538 [doi]

2008

A Low-Cost Programmable Memory BIST Design for Multiple Memory InstancesChung-Fu Lin, Chia-Fu Huang, De-Chung Lu, Chih-Chiang Hsu, Wen-Tsung Chiu, Yu-Wei Chen, Yeong-Jar Chang. itc 2008: 1 [doi]

2005

Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia PrincipleMing Shae Wu, Chung-Len Lee, Yeong-Jar Chang, Wen Ching Wu. ats 2005: 106-111 [doi]

2004

2000

A Behavior-Level Fault Model for the Closed-Loop Operational AmplifierYeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su. jise, 16(5):751-766, 2000. [doi]

1994

Synthesis of Multi-Variable MVL Funtions Using Hybrid Mode CMOS LogicYeong-Jar Chang, Chung-Len Lee. ismvl 1994: 35-41

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