Table of Contents

• High density 3D integration by pre-applied Inter Chip FillAkihiro Horibe, Kuniaki Sueoka, Katsuyuki Sakuma, Sayuri Kohara, Keiji Matsumoto, Hidekazu Kikuchi, Yasumitsu Orii, Toshiro Mitsuhashi, Fumiaki Yamada. 1-5 [doi]
• A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systemsGil-Su Kim, Katsuyuki Ikeuchi, Mutsuo Daito, Makoto Takamiya, Takayasu Sakurai. 1-4 [doi]
• A block-parallel signal processing system for CMOS image sensor with three-dimensional structureKouji Kiyoyama, Kang-Wook Lee, Takafumi Fukushima, H. Naganuma, Hiroaki Kobayashi, Tetsu Tanaka, Mitsumasa Koyanagi. 1-4 [doi]
• Design platform and tools for 3D IC integrationKholdoun Torki. 1-25 [doi]
• Pixel detectors in 3D technologies for high energy physicsGrzegorz Deptuch, Marcel Demarteau, Jim Hoff, Ronald Lipton, Alpana Shenai, Raymond Yarema, Tom Zimmerman. 1-4 [doi]
• Crosstalk evaluation, suppression and modeling in 3D through-strata-via (TSV) networkZheng Xu, Adam Beece, Dingyou Zhang, Qianwen Chen, Kuan-Neng Chen, Kenneth Rose, Jian-Qiang Lu. 1-8 [doi]
• Wireless power transfer using resonant inductive coupling for 3D integrated ICsSangwook Han, David D. Wentzloff. 1-5 [doi]
• Equipment challenges and solutions for diverse temporary bonding and de-bonding processes in 3D integrationMarkus Gabriel, Thomas Knauer, Peter Bisson, Sumant Sood, Wilfried Bair, Jim Hermanowski. 1-5 [doi]
• 3D ICs and pixel sensors: The Italian VIPIX project and the European AIDA WP3 projectValerio Re. 1-6 [doi]
• Performance analysis of 3-D monolithic integrated circuitsShashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Vasilis F. Pavlidis, Giovanni De Micheli. 1-4 [doi]
• A novel concept for ultra-low capacitance via-last TSVYann Civale, Marcel Gonzalez, Deniz Sabuncuoglu Tezcan, Youssef Travaly, Philippe Soussan, Eric Beyne. 1-4 [doi]
• Cache partitioning strategies for 3-D stacked vector processorsYusuke Funaya, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi. 1-6 [doi]
• Development of high accuracy wafer thinning and pickup technology for thin waferChuichi Miyazaki, Haruo Shimamoto, Toshihide Uematsu, Yoshiyuki Abe, Kosuke Kitaichi, Tadahiro Morifuji, Shoji Yasunaga. 1-4 [doi]
• Real-time thermal management of 3D multi-core system with fine-grained cooling controlHanhua Qian, Xiwei Huang, Hao Yu, Chip-Hong Chang. 1-6 [doi]
• A 3D SoC design for H.264 application with on-chip DRAM stackingTao Zhang, Kui Wang, Yi Feng 0003, Yan Chen, Qun Li, Bing Shao, Jing Xie, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin. 1-6 [doi]
• Solution space investigation and comparison of modern data structures for heterogeneous 3D designsRobert Fischbach, Jens Lienig, Matthias Thiele. 1-8 [doi]
• 3DIC multi-project-wafer program: A collaboration to provide fabrication accessVance Tyree. 1-17 [doi]
• Cost effectiveness of 3D integration optionsDimitrios Velenis, Erik Jan Marinissen, Eric Beyne. 1-6 [doi]
• 3D memory stacking for fast checkpointing/restore applicationsJing Xie, Xiangyu Dong, Yuan Xie. 1-6 [doi]
• Integration of multi physics modeling of 3D stacks into modern 3D data structuresPeter Schneider, Andy Heinig, Robert Fischbach, Jens Lienig, Sven Reitz, Jörn Stolle, Andreas Wilde. 1-6 [doi]
• Timing analysis and optimization for 3D stacked multi-core microprocessorsYoung-Joon Lee, Sung Kyu Lim. 1-7 [doi]
• TSV development for miniaturized MEMS acceleration switchNicolas Lietaer, Anand Summanwar, Thor Bakke, Maaike Taklo, Per Dalsjø. 1-4 [doi]
• 3D stacked buck converter with 15μm thick spiral inductor on silicon interposer for fine-grain power-supply voltage control in SiP sKoichi Ishida, Koichi Takemura, Kazuhiro Baba, Makoto Takamiya, Takayasu Sakurai. 1-4 [doi]
• Silicon-interposer with high density Cu-filled TSVsRobert Wieland, Kai Zoschke, Nils Jurgensen, Karl-Reinhard Merkel, Lars Nebrich, Jürgen Wolf. 1-4 [doi]
• A successful implementation of dual damascene architecture to copper TSV for 3D high density applicationsRebha El Farhane, Myriam Assous, Patrick Leduc, Aurélie Thuaire, David Bouchu, Hélène Feldis, Nicolas Sillon. 1-4 [doi]
• Application of the SLID-ICV interconnection technology for the ATLAS pixel upgrade at SLHCLadislav Andricek, Michael Beimforde, Armin Klumpp, Anna Macchiolo, Karl-Reinhard Merkel, Hans-Günther Moser, Richard Nisius, Rainer Helmut Richter, Josef Weber, Philipp Weigell, Robert Wieland. 1-4 [doi]
• 3D integration - A server perspectiveJeff Burns. 1-20 [doi]
• The NCSU Tezzaron design kitSteve Lipa, Thorlindur Thorolfsson, Paul D. Franzon. 1-15 [doi]
• High sensitivity fully digital photodetectorJean-François Pratte, Marc-André Tétrault, Réjean Fontaine. 1-9 [doi]
• Through Silicon photonic via (TSPV) with Si core for low loss and high-speed data transmission in opto-electronic 3-D LSIAkihiro Noriki, Kang-Wook Lee, Jichoel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi. 1-4 [doi]
• Wafer-level 3D integration using hybrid bondingCheng-Ta Ko, Kuan-Neng Chen, Wei-Chung Lo, Chuan-An Cheng, Wen-Chun Huang, Zhi-Cheng Hsiao, Huan-Chun Fu, Yu-Hua Chen. 1-4 [doi]
• Additive interconnect fabrication by picosecond Laser Induced Forward TransferGerrit Oosterhuis, Bert Huis in 't Veld, Gerald Ebberink, Daniël Arnaldo del Cerro, Edwin van den Eijnden, Peter Chall, Ben van der Zon. 1-5 [doi]
• 3D system on chip memory interface based on modeled capacitive coupling interconnectionsMauro Scandiuzzo, Roberto Cardu, Salvatore Cani, Simone Spolzino, Luca Perugini, Eleonora Franchi, Roberto Canegallo, Roberto Guerrieri. 1-4 [doi]
• Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperatureTakafumi Fukushima, Eiji Iwata, Jichoel Bea, Mariappan Murugesan, Kang-Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi. 1-5 [doi]
• Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integrationKiyoto Ito, Makoto Saen, Kenichi Osada, Tomoyuki Kodama, Hiroyuki Mizuno. 1-6 [doi]
• 3DIC multi-project fabrication run being organized by CMC/CMP/MOSIS and TezzaronGrzegorz Deptuch. 1-10 [doi]
• CMIT - A novel cluster-based topology for 3D stacked architecturesMasoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 1-5 [doi]
• Logic-on-logic 3D integration and placementThorlindur Thorolfsson, Guojie Luo, Jason Cong, Paul D. Franzon. 1-4 [doi]
• Developing digital test sequences for through-silicon vias within 3D structuresMatthias Gulbins, Fabian Hopsch, Peter Schneider, Bernd Straube, Wolfgang Vermeiren. 1-6 [doi]
• Thermal isolation in 3D chip stacks using vacuum gaps and capacitive or inductive communicationsPaul D. Franzon, John Wilson, Ming Li. 1-4 [doi]
• 3D heterogeneous integration for novel functionalityMontserrat Fernandez-Bolaños, Adrian M. Ionescu. 1-19 [doi]
• High performance 3D interconnects based on electrochemical etch and liquid metal fillHarry Hedler, Thomas Scheiter, Markus Schieber, Armin Klumpp, Peter Ramm. 1-7 [doi]
• A study of IR-drop noise issues in 3D ICs with through-silicon-viasMoongon Jung, Sung Kyu Lim. 1-7 [doi]
• Monolithic 3D integration of SRAM and image sensor using two layers of single grain siliconNegin Golshani, Jaber Derakhshandeh, Ryoichi Ishihara, C. I. M. Beenakker, Michael Robertson, Thomas Morrison. 1-4 [doi]
• 3D DfT architecture for pre-bond and post-bond testingErik Jan Marinissen, Chun-Chuan Chi, Jouke Verbree, Mario H. Konijnenburg. 1-8 [doi]
• Development of a CAD tool for 3D-FPGAsNaoto Miyamoto, Yohei Matsumoto, Hanpei Koike, Tadayuki Matsumura, Kenichi Osada, Yaoko Nakagawa, Tadahiro Ohmi. 1-6 [doi]
• Early estimation of TSV area for power delivery in 3-D integrated circuitsNauman H. Khan, Sherief Reda, Soha Hassoun. 1-6 [doi]
• Enabling power distribution network analysis flows for 3D ICsXiang Hu, Thomas Toms, Riko Radojcic, Matt Nowak, Nick Yu, Chung-Kuan Cheng. 1-4 [doi]
• Reliability testing of high aspect ratio through silicon vias fabricated with atomic layer deposition barrier, seed layer and direct plating and material properties characterization of electrografted insulator, barrier and seed layer for 3-D integrationJason D. Reed, Scott Goodwin, Christopher Gregory, Dorota Temple. 1-8 [doi]
• Wafer-level hybrid bonding technology with copper/polymer co-planarizationMayu Aoki, Kazuyuki Hozawa, Kenichi Takeda. 1-4 [doi]
• Recent Developments of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stackingIonut Radu, Didier Landru, Gweltaz Gaudin, Gregory Riou, Catherine Tempesta, F. Letertre, Léa Di Cioccio, Pierric Gueguen, Thomas Signamarcheix, C. Euvrard, Jérôme Dechamp, Laurent Clavelier, Mariam Sadaka. 1-6 [doi]
• Use of optical metrology for wafer level packaging of CMOS image sensorD. Le Cunff, A. Pravdivtsev, K. Le Chao, C. Euvrard, E. Deloffre, A. Cailean. 1-6 [doi]
• Power delivery network design and optimization for 3D stacked die designsPratyush Singh, R. Sankar, Xiang Hu, Weize Xie, Aveek Sarkar, Thomas Toms. 1-6 [doi]
• All-wet fabrication technology for high aspect ratio TSV using electroless barrier and seed layersFumihiro Inoue, Takumi Yokoyama, Hiroshi Miyake, Shukichi Tanaka, Toshifumi Terui, Tomohiro Shimizu, Shoso Shingubara. 1-5 [doi]
• Fabrication of TSV-based silicon interposersDean Malta, Erik Vick, Scott Goodwin, Christopher Gregory, Matthew Lueck, Alan Huffman, Dorota Temple. 1-6 [doi]
• Low temperature direct wafer to wafer bonding for 3D integration: Direct bonding, surface preparation, wafer-to-wafer alignmentGweltaz Gaudin, Gregory Riou, Didier Landru, Catherine Tempesta, Ionut Radu, Mariam Sadaka, Kevin Winstel, Emily Kinser, Robert Hannon. 1-4 [doi]
• Impact of microbump induced stress in thinned 3D-LSIs after wafer bondingMariappan Murugesan, Yuki Ohara, Jichoel Bea, Kang-Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi. 1-5 [doi]
• Fine-pitch bump-less Cu-Cu bonding for wafer-on-wafer stacking and its quality enhancementLan Peng, HongYu Li, Dau Fatt Lim, Riko I. Made, Guo-Qiang Lo, Dim-Lee Kwong, Chuan Seng Tan. 1-5 [doi]
• 300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applicationsAnne Jourdain, Thibault Buisson, Alain Phommahaxay, Mark Privett, Dan Wallace, Sumant Sood, Peter Bisson, Eric Beyne, Youssef Travaly, Bart Swinnen. 1-4 [doi]
• Design and early evaluation of a 3-D die stacked chip multi-vector processorRyusuke Egawa, Yusuke Funaya, Ryu-ichi Nagaoka, Akihiro Musa, Hiroyuki Takizawa, Hiroaki Kobayashi. 1-8 [doi]
• In-pixel ADC for a vision architecture on CMOS-3D technologyManuel Suarez, Victor Manuel Brea, Carlos M. Domínguez-Matas, Ricardo Carmona, Gustavo Liñán, Ángel Rodríguez-Vázquez. 1-7 [doi]
• Post-bond sub-500 nm alignment in 300 mm integrated face-to-face wafer-to-wafer Cu-Cu thermocompression, Si-Si fusion and oxideoxide fusion bondingWeng Hong Teh, C. Deeb, J. Burggraf, D. Arazi, R. Young, C. Senowitz, A. Buxbaum. 1-6 [doi]
• Pre bonding metrology solutions for 3D integrationGregory Riou, Gweltaz Gaudin, Didier Landru, Catherine Tempesta, Ionut Radu, Mariam Sadaka, Kevin Winstel, Emily Kinser, Robert Hannon, Boris V. Kamenev, Michael Darwin, Robert Sachs. 1-5 [doi]