Abstract is missing.
- Message from the General Chair [doi]
- Reviewers [doi]
- Committees [doi]
- Tutorials and Workshops [doi]
- Message from the Program Chair [doi]
- Multi-Core to the MassesJustin R. Rattner. 3 [doi]
- Variational Path ProfilingErez Perelman, Trishul M. Chilimbi, Brad Calder. 7-16 [doi]
- Extended Whole Program PathsSriraman Tallam, Rajiv Gupta, Xiangyu Zhang. 17-26 [doi]
- Instruction Based Memory Distance Analysis and its ApplicationChangpeng Fang, Steve Carr, Soner Önder, Zhenlin Wang. 27-37 [doi]
- HPS: Hybrid Profiling SupportHussam Mousa, Chandra Krintz. 38-50 [doi]
- Maximizing CMP Throughput with Mediocre CoresJohn D. Davis, James Laudon, Kunle Olukotun. 51-62 [doi]
- Characterization of TCC on Chip-MultiprocessorsAusten McDonald, JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Brian D. Carlstrom, Lance Hammond, Christos Kozyrakis, Kunle Olukotun. 63-74 [doi]
- Store-Ordered Streaming of Shared MemoryThomas F. Wenisch, Stephen Somogyi, Nikolaos Hardavellas, Jangwoo Kim, Chris Gniady, Anastassia Ailamaki, Babak Falsafi. 75-86 [doi]
- An Event-Driven Multithreaded Dynamic Optimization FrameworkWeifeng Zhang, Brad Calder, Dean M. Tullsen. 87-98 [doi]
- Design and Implementation of a Compiler Framework for Helper Threading on Multi-core ProcessorsYonghong Song, Spiros Kalogeropulos, Partha Tirumalai. 99-109 [doi]
- Compiler Directed Early Register ReleaseTimothy M. Jones, Michael F. P. O Boyle, Jaume Abella, Antonio González, Oguz Ergin. 110-122 [doi]
- Automatic Selection of Compiler Options Using Non-parametric Inferential StatisticsMasayo Haneda, Peter M. W. Knijnenburg, Harry A. G. Wijshoff. 123-132 [doi]
- Data Centric Transformations on Non-Integer Iteration SpacesSwarup Kumar Sahoo, Gagan Agrawal. 133-142 [doi]
- Efficient Techniques for Advanced Data Dependence AnalysisKonstantinos Kyriakopoulos, Kleanthis Psarris. 143-156 [doi]
- Parallel Programming and Parallel Abstractions in FortressGuy L. Steele Jr.. 157 [doi]
- Optimizing Compiler for the CELL ProcessorAlexandre E. Eichenberger, Kathryn M. O Brien, Kevin O Brien, Peng Wu, Tong Chen, Peter H. Oden, Daniel A. Prener, Janice C. Shepherd, Byoungro So, Zehra Sura, Amy Wang, Tao Zhang, Peng Zhao, Michael Gschwind. 161-172 [doi]
- Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding with a Network ProcessorBen Wun, Jeremy Buhler, Patrick Crowley. 173-184 [doi]
- Automatic Tuning Matrix Multiplication Performance on Graphics HardwareChanghao Jiang, Marc Snir. 185-196 [doi]
- A Distributed Control Path Architecture for VLIW ProcessorsHongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael S. Schlansker. 197-206 [doi]
- Variable-Based Multi-module Data Caches for Clustered VLIW ProcessorsEnric Gibert, Jaume Abella, F. Jesús Sánchez, Xavier Vera, Antonio González. 207-217 [doi]
- Performance Analysis of System Overheads in TCP/IP WorkloadsNathan L. Binkert, Lisa R. Hsu, Ali G. Saidi, Ronald G. Dreslinski, Andrew L. Schultz, Steven K. Reinhardt. 218-230 [doi]
- Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction WindowHuiyang Zhou. 231-242 [doi]
- A Simple Divide-and-Conquer Approach for Neural-Class Branch PredictionGabriel H. Loh. 243-254 [doi]
- Trace Cache Sampling FilterMichael Behar, Avi Mendelson, Avinoam Kolodny. 255-266 [doi]
- Communication Optimizations for Fine-Grained UPC ApplicationsWei-Yu Chen, Costin Iancu, Katherine A. Yelick. 267-278 [doi]
- HUNTing the OverlapCostin Iancu, Parry Husbands, Paul Hargrove. 279-290 [doi]
- Deep Jam: Conversion of Coarse-Grain Parallelism to Instruction-Level and Vector Parallelism for Irregular ApplicationsPatrick Carribault, Albert Cohen, William Jalby. 291-302 [doi]
- Memory State Compressors for Giga-Scale Checkpoint/RestoreAndreas Moshovos, Alexandros Kostopoulos. 303-314 [doi]
- Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault ToleranceM. Wasiur Rashid, Edwin J. Tan, Michael C. Huang, David H. Albonesi. 315-328 [doi]
- Memory Coloring: A Compiler Approach for Scratchpad Memory ManagementLian Li 0002, Lin Gao 0002, Jingling Xue. 329-338 [doi]
- Multiple Page Size Modeling and OptimizationCalin Cascaval, Evelyn Duesterwald, Peter F. Sweeney, Robert W. Wisniewski. 339-349 [doi]
- Future Execution: A Hardware Prefetching Technique for Chip MultiprocessorsIlya Ganusov, Martin Burtscher. 350-360 [doi]