Amitava Majumdar, Balakrishna Jayadev, Da Cheng, Albert Lin. Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs. In 26th IEEE Asian Test Symposium, ATS 2017, Taipei City, Taiwan, November 27-30, 2017. pages 139-144, IEEE Computer Society, 2017. [doi]
Abstract is missing.