High-speed low-area-cost VLSI design of polar codes encoder architecture using radix-k processing engines

Xin-Yu Shih, Po-Chun Huang, Yu-Chun Chen. High-speed low-area-cost VLSI design of polar codes encoder architecture using radix-k processing engines. In IEEE 5th Global Conference on Consumer Electronics, GCCE 2016, Kyoto, Japan, October 11-14, 2016. pages 1-2, IEEE, 2016. [doi]

Abstract

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