Table of Contents

• Deep Learning Based Test Compression AnalyzerCheng-Hung Wu, Yu Huang 0005, Kuen-Jong Lee, Wu-Tung Cheng, Gaurav Veda, Sudhakar M. Reddy, Chun-Cheng Hu, Chong-Siao Ye. 1-6 [doi]
• Sanity-Check: Boosting the Reliability of Safety-Critical Deep Neural Network ApplicationsElbruz Ozen, Alex Orailoglu. 7-12 [doi]
• Applying Neural Networks to Delay Fault Testing: Test Point Insertion and Random Circuit TrainingSpencer K. Millican, Yang Sun, Soham Roy, Vishwani D. Agrawal. 13-18 [doi]
• TEA: A Test Generation Algorithm for Designs with Timing ExceptionsNaixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, Xijiang Lin, Mark Kassab, Irith Pomeranz. 19-24 [doi]
• Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-TestManobendra Nath Mondal, Animesh Basak Chowdhury, Manjari Pradhan, Susmita Sur-Kolay, Bhargab B. Bhattacharya. 25-30 [doi]
• A Built-In Self-Diagnostic Mechanism for Delay Faults Based on Self-Generation of Expected SignaturesYushiro Hiramoto, Satoshi Ohtake, Hiroshi Takahashi. 31-36 [doi]
• Self-Checking Residue Number System for Low-Power Reliable Neural NetworkTsung-Chu Huang. 37-42 [doi]
• Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial ApplicationsAibin Yan, Zhen Wu, Lu Lu, Zhili Chen, Jie Song, Zuobin Ying, Patrick Girard 0001, Xiaoqing Wen. 43-48 [doi]
• Machine Learning Assisted Accurate Estimation of Usage Duration and Manufacturer for Recycled and Counterfeit Flash Memory DetectionSaranyu Chattopadhyay, Preeti Kumari, Biswajit Ray, Rajat Subhra Chakraborty. 49-54 [doi]
• Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial ApplicationsAibin Yan, Zhen Wu, Jun Zhou, Yuanjie Hu, Yan Chen, Zuobin Ying, Xiaoqing Wen, Patrick Girard 0001. 55-60 [doi]
• Can Monitoring System State + Counting Custom Instruction Sequences Aid Malware Detection?Aditya Rohan, Kanad Basu, Ramesh Karri. 61-66 [doi]
• Reinforcement-Learning-Based Test Program Generation for Software-Based Self-TestChing-Yuan Chen, Jiun-Lang Huang. 73-78 [doi]
• Latency Aware Fault Tolerant Cache in Multicore Using Dynamic Remapping ClustersAvishek Choudhury, Brototi Mondal, Biplab K. Sikdar. 79 [doi]
• Recruiting Fault Tolerance Techniques for Microprocessor SecurityVinay B. Y. Kumar, Suman Deb, Rupesh Kumar, Mustafa Khairallah, Anupam Chattopadhyay, Avi Mendelson. 80-85 [doi]
• Deep Learning Based Diagnostics for Rowhammer Protection of DRAM ChipsAnirban Chakraborty, Manaar Alam, Debdeep Mukhopadhyay. 86-91 [doi]
• Towards Verifiably Secure Systems-on-Chip PlatformsSujit Kumar Muduli, Pramod Subramanyan. 92-97 [doi]
• Machine-Learning-Based Multiple Abstraction-Level Detection of Hardware Trojan Inserted at Register-Transfer LevelHau Sim Choo, Chia Yee Ooi, Michiko Inoue, Nordinah Ismail, Mehrdad Moghbel, Sreedharan Baskara Dass, Chee Hoo Kok, Fawnizu Azmadi Hussin. 98 [doi]
• Validating Multi-Processor Cache Coherence Mechanisms under Diminished ObservabilityBinod Kumar 0001, Atul Kumar Bhosale, Masahiro Fujita, Virendra Singh. 99-104 [doi]
• Net Classification Based on Testability and Netlist Structural Features for Hardware Trojan DetectionChee Hoo Kok, Chia Yee Ooi, Michiko Inoue, Mehrdad Moghbel, Sreedharan Baskara Dass, Hau Sim Choo, Nordinah Ismail, Fawnizu Azmadi Hussin. 105-110 [doi]
• GramsDet: Hardware Trojan Detection Based on Recurrent Neural NetworkRenjie Lu, Haihua Shen, Yu Su, Huawei Li, Xiaowei Li 0001. 111-116 [doi]
• Efficient Testing of Physically Unclonable Functions for UniquenessLeandro Santiago de Araújo, Vinay C. Patil, Leandro Augusto Justen Marzulo, Felipe Maia Galvão França, Sandip Kundu. 117-122 [doi]
• Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal VerificationVineesh V. S., Binod Kumar 0001, Rushikesh Shinde, Akshay Jaiswal, Harsh Bhargava, Virendra Singh. 123-128 [doi]
• Combining Fault Analysis Technologies for ISO26262 Functional Safety VerificationFelipe Augusto da Silva, Ahmet Cagri Bagbaba, Said Hamdioui, Christian Sauer 0001. 129-134 [doi]
• A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog CircuitsSayandeep Sanyal, Amit Patra, Pallab Dasgupta, Mayukh Bhattacharya. 135-140 [doi]
• Hierarchical State Space Checks for Errors in Sensors, Actuators and Control of Nonlinear Systems: Diagnosis and CompensationMd Imran Momtaz, Abhijit Chatterjee. 141-146 [doi]
• Iterative Parallel Test to Detect and Diagnose Multiple Defects for Digital Microfluidic BiochipSourav Ghosh, Dolan Maity, Arijit Chowdhury, Surajit Kumar Roy, Chandan Giri. 147-152 [doi]
• Detailed Fault Model for Physical Quantum CircuitsArighna Deb, Debesh K. Das. 153-158 [doi]
• Ensuring Correctness of Next Generation Devices: From Reconfigurable to Self-Learning SystemsRolf Drechlser, Daniel Große. 159-164 [doi]