Table of Contents

• Differentiate and deliver: leveraging your partnersJay Vleeschhouwer, Warren East, Michael J. Fister, Aart J. de Geus, Walden C. Rhines, Jackson Hu, Rick Cassidy. 1 [doi]
• Logic soft errors in sub-65nm technologies design and CAD challengesSubhasish Mitra, Tanay Karnik, Norbert Seifert, Ming Zhang. 2-4 [doi]
• SEU tolerant device, circuit and processor designWilliam Heidergott. 5-10 [doi]
• Variability and energy awareness: a microarchitecture-level perspectiveDiana Marculescu, Emil Talpes. 11-16 [doi]
• Energy-effcient physically tagged caches for embedded processors with virtual memoryPeter Petrov, Daniel Tracy, Alex Orailoglu. 17-22 [doi]
• Hybrid simulation for embedded software energy estimationAnish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha. 23-26 [doi]
• Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable designPatrick Schaumont, Bo-Cheng Charles Lai, Wei Qin, Ingrid Verbauwhede. 27-30 [doi]
• Total power reduction in CMOS circuits via gate sizing and multiple threshold voltagesFeng Gao, John P. Hayes. 31-36 [doi]
• An effective power mode transition technique in MTCMOS circuitsAfshin Abdollahi, Farzan Fallah, Massoud Pedram. 37-42 [doi]
• A self-adjusting scheme to determine the optimum RBB by monitoring leakage currentsNikhil Jayakumar, Sandeep Dhar, Sunil P. Khatri. 43-46 [doi]
• Enhanced leakage reduction Technique by gate replacementLin Yuan, Gang Qu. 47-50 [doi]
• Automated nonlinear Macromodelling of output buffers for high-speed digital applicationsNing Dong, Jaijeet S. Roychowdhury. 51-56 [doi]
• Systematic development of analog circuit structural macromodels through behavioral model decouplingYing Wei, Alex Doboli. 57-62 [doi]
• A combined feasibility and performance macromodel for analog circuitsMengmeng Ding, Ranga Vemuri. 63-68 [doi]
• ESL: building the bridge between systems to siliconFrancine Bacchini, David Maliniak, Terry Doherty, Peter McShane, Suhas A. Pai, Sriram Sundararajan, Soo-Kwan Eo, Pascal Urard. 69-70 [doi]
• Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functionsHongliang Chang, Vladimir Zolotov, Sambasivan Narayan, Chandu Visweswariah. 71-76 [doi]
• Correlation-aware statistical timing analysis with non-gaussian delay distributionsYaping Zhan, Andrzej J. Strojwas, Xin Li, Lawrence T. Pileggi, David Newmark, Mahesh Sharma. 77-82 [doi]
• Correlation-preserved non-gaussian statistical timing analysis with quadratic timing modelLizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen. 83-88 [doi]
• A general framework for accurate statistical timing analysis considering correlationsVishal Khandelwal, Ankur Srivastava. 89-94 [doi]
• Locality-conscious workload assignment for array-based computations in MPSOC architecturesFeihui Li, Mahmut T. Kandemir. 95-100 [doi]
• Automatic scenario detection for improved WCET estimationStefan Valentin Gheorghita, Sander Stuijk, Twan Basten, Henk Corporaal. 101-104 [doi]
• Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system designJungeun Kim, Taewhan Kim. 105-110 [doi]
• Dynamic slack reclamation with procrastination scheduling in real-time embedded systemsRavindra Jejurikar, Rajesh K. Gupta. 111-116 [doi]
• Response compaction with any number of unknowns using a new LFSR architectureErik H. Volkerink, Subhasish Mitra. 117-122 [doi]
• Multi-frequency wrapper design and optimization for embedded cores under average power constraintsQiang Xu, Nicola Nicolici, Krishnendu Chakrabarty. 123-128 [doi]
• N-detection under transparent-scanIrith Pomeranz. 129-134 [doi]
• Secure scan: a design-for-test architecture for crypto chipsBo Yang, Kaijie Wu, Ramesh Karri. 135-140 [doi]
• A green function-based parasitic extraction method for inhomogeneous substrate layersChenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram. 141-146 [doi]
• Analysis of full-wave conductor system impedance over substrate using novel integration techniquesXin Hu, Jung Hoon Lee, Jacob White, Luca Daniel. 147-152 [doi]
• Spatially distributed 3D circuit modelsMichael W. Beattie, Hui Zheng, Anirudh Devgan, Byron Krauter. 153-158 [doi]
• DiMES: multilevel fast direct solver based on multipole expansions for parasitic extraction of massively coupled 3D microelectronic structuresDipanjan Gope, Indranil Chowdhury, Vikram Jandhyala. 159-162 [doi]
• ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extractionRong Jiang, Yi-Hao Chang, Charlie Chung-Ping Chen. 163-166 [doi]
• Choosing flows and methodologies for SoC designDennis Wassung, Yervant Zorian, Magdy S. Abadir, Mark Bapst, Colin Harris. 167 [doi]
• DFM rules!Naveed A. Sherwani, Susan Lippincott Mack, Alex Alexanian, Premal Buch, Carlo Guardiani, Harold Lehon, Peter Rabkin, Atul Sharan. 168-169 [doi]
• Partitioning-based approach to fast on-chip decap budgeting and minimizationHang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong. 170-175 [doi]
• Navigating registers in placement for clock network minimizationYongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu. 176-181 [doi]
• Minimizing peak current via opposite-phase clock treeYow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu. 182-185 [doi]
• A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysisHaihua Su, David Widiger, Chandramouli V. Kashyap, Frank Liu, Byron Krauter. 186-189 [doi]
• Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuitsChong Zhao, Yi Zhao, Sujit Dey. 190-195 [doi]
• Temperature-aware resource allocation and binding in high-level synthesisRajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Memik. 196-201 [doi]
• Leakage power optimization with dual-V::th:: library in high-level synthesisXiaoyong Tang, Hai Zhou, Prithviraj Banerjee. 202-207 [doi]
• Incremental exploration of the combined physical and behavioral design spaceZhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou. 208-213 [doi]
• Sign bit reduction encoding for low power applicationsM. Saneei, Ali Afzali-Kusha, Zainalabedin Navabi. 214-217 [doi]
• A watermarking system for IP protection by a post layout incremental routerTingyuan Nie, Tomoo Kisaka, Masahiko Toyonaga. 218-221 [doi]
• A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processingKris Tiri, David Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede. 222-227 [doi]
• Simulation models for side-channel information leaksKris Tiri, Ingrid Verbauwhede. 228-233 [doi]
• A pattern matching coprocessor for network securityYoung H. Cho, William H. Mangione-Smith. 234-239 [doi]
• High performance encryption cores for 3G networksTomás Balderas-Contreras, René Cumplido. 240-243 [doi]
• Efficient fingerprint-based user authentication for embedded systemsPallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. 244-247 [doi]
• Approximate VCCs: a new characterization of multimedia workloads for system-level MpSoC designYanhong Liu, Samarjit Chakraborty, Wei Tsang Ooi. 248-253 [doi]
• Modular domain-specific implementation and exploration framework for embedded software platformsChristian Sauer, Matthias Gries, Sören Sonntag. 254-259 [doi]
• Simulation based deadlock analysis for system level designsXi Chen, Abhijit Davare, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe. 260-265 [doi]
• Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoCSorin Manolache, Petru Eles, Zebo Peng. 266-269 [doi]
• High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trade-offsAndrey V. Zykov, Elias Mizan, Margarida F. Jacome, Gustavo de Veciana, Ajay Subramanian. 270-273 [doi]
• How to determine the necessity for emerging solutionsNic Mokhoff, Yervant Zorian, Kamalesh N. Ruparel, Hao Nham, Francesco Pessolano, Kee Sup Kim. 274-275 [doi]
• Closing the power gap between ASIC and custom: an ASIC perspectiveDavid G. Chinnery, Kurt Keutzer. 275-280 [doi]
• Explaining the gap between ASIC and custom power: a custom perspectiveAndrew Chang, William J. Dally. 281-284 [doi]
• Keeping hot chips coolRuchir Puri, Leon Stok, Subhrajit Bhattacharya. 285-288 [doi]
• Interconnects are moving from MHz->GHz should you be afraid?: or... my giga hertz, does yours? Navraj Nandra, Phil Dworsky, Rick Merritt, John F. D Ambrosia, Adam Healey, Boris Litinsky, John Stonick, Joe Abler. 289-290 [doi]
• Design methodology for wireless nodes with printed antennasJean-Samuel Chenard, Chun Yiu Chu, Zeljko Zilic, Milica Popovic. 291-296 [doi]
• MP core: algorithm and design techniques for efficient channel estimation in wireless applicationsYan Meng, Andrew P. Brown, Ronald A. Iltis, Timothy Sherwood, Hua Lee, Ryan Kastner. 297-302 [doi]
• From myth to methodology: cross-layer design for energy-efficient wireless communicationWolfgang Eberle, Bruno Bougard, Sofie Pollin, Francky Catthoor. 303-308 [doi]
• An efficient algorithm for statistical minimization of total power under timing yield constraintsMurari Mani, Anirudh Devgan, Michael Orshansky. 309-314 [doi]
• Robust gate sizing by geometric programmingJaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, Sachin S. Sapatnekar. 315-320 [doi]
• Circuit optimization using statistical static timing analysisAseem Agarwal, Kaviraj Chopra, David Blaauw, Vladimir Zolotov. 321-324 [doi]
• An exact jumper insertion algorithm for antenna effect avoidance/fixingBor-Yiing Su, Yao-Wen Chang. 325-328 [doi]
• Fine-grained application source code profiling for ASIP designKingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr. 329-334 [doi]
• Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfigurationSudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt. 335-340 [doi]
• Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuseHo Young Kim, Tag Gon Kim. 341-344 [doi]
• Trace-driven HW/SW cosimulation using virtual synchronization techniqueDohyung Kim, Youngmin Yi, Soonhoi Ha. 345-348 [doi]
• The Titanic: what went wrong!Sani R. Nassif, Paul S. Zuchowski, Claude Moughanni, Mohamed Moosa, Stephen D. Posluszny, Ward Vercruysse. 349-350 [doi]
• Wireless platforms: GOPS for cents and MilliWattsFrancine Bacchini, Jan M. Rabaey, Allan Cox, Frank Lane, Rudy Lauwereins, Ulrich Ramacher, David Witt. 351-352 [doi]
• Design methodology for IC manufacturability based on regular logic-bricksV. Kheterpal, V. Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi. 353-358 [doi]
• Advanced timing analysis based on post-OPC extraction of critical dimensionsJie Yang, Luigi Capodieci, Dennis Sylvester. 359-364 [doi]
• Advanced Timing Analysis Based on Post-OPC Extraction of Critical DimensionsPuneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester. 365-368 [doi]
• RADAR: RET-aware detailed routing using fast lithography simulationsJoydeep Mitra, Peng Yu, David Zhigang Pan. 369-372 [doi]
• BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decompositionTsutomu Sasao, Munehiro Matsuura. 373-378 [doi]
• A new canonical form for fast boolean matching in logic synthesis and verificationAfshin Abdollahi, Massoud Pedram. 379-384 [doi]
• Effective bounding techniques for solving unate and binate covering problemsXiao Yu Li, Matthias F. M. Stallmann, Franc Brglez. 385-390 [doi]
• Operator-based model-order reduction of linear periodically time-varying systemsYayun Wan, Jaijeet S. Roychowdhury. 391-396 [doi]
• Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuitsV. Vasudevan. 397-402 [doi]
• Scalable trajectory methods for on-demand analog macromodel extractionSaurabh K. Tiwary, Rob A. Rutenbar. 403-408 [doi]
• Cognitive radio techniques for wide area networksWilliam Krenik, Anuj Batra. 409-412 [doi]
• MIMO technology for advanced wireless local area networksJeffrey M. Gilbert, Won-Joon Choi, Qinfang Sun. 413-415 [doi]
• RF MEMS in wireless architecturesClark T.-C. Nguyen. 416-420 [doi]
• Multiplexer restructuring for FPGA implementation cost reductionPaul Metzgen, Dominic Nancekievill. 421-426 [doi]
• FPGA technology mapping: a study of optimalityAndrew C. Ling, Deshanand P. Singh, Stephen Dean Brown. 427-432 [doi]
• Incremental retiming for FPGA physical synthesisDeshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown. 433-438 [doi]
• Architecture-adaptive range limit windowing for simulated annealing FPGA placementKenneth Eguro, Scott Hauck, Akshay Sharma. 439-444 [doi]
• Word level predicate abstraction and refinement for verifying RTL verilogHimanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke. 445-450 [doi]
• Structural search for RTL with predicate learningGanapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer. 451-456 [doi]
• Normalization at the arithmetic bit levelMarkus Wedler, Dominik Stoffel, Wolfgang Kunz. 457-462 [doi]
• Exploiting suspected redundancy without proving itHari Mony, Jason Baumgartner, Viresh Paruthi, Robert Kanzelman. 463-466 [doi]
• Multi-threaded reachabilityDebashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson. 467-470 [doi]
• Automatic generation of customized discrete fourier transform IPsGrace Nordin, Peter A. Milder, James C. Hoe, Markus Püschel. 471-474 [doi]
• Race-condition-aware clock skew schedulingShih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu. 475-478 [doi]
• A novel synthesis approach for active leakage power reduction using dynamic supply gatingSwarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy. 479-484 [doi]
• Designing logic circuits for probabilistic computation in the presence of noiseKundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky. 485-490 [doi]
• A lattice-based framework for the classification and design of asynchronous pipelinesPeggy B. McGee, Steven M. Nowick. 491-496 [doi]
• Power optimal dual-Vdd buffered tree considering buffer stations and blockagesKing Ho Tam, Lei He. 497-502 [doi]
• Net weighting to reduce repeater counts during placementBrent Goplen, Prashant Saxena, Sachin S. Sapatnekar. 503-508 [doi]
• Path based buffer insertionCliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi. 509-514 [doi]
• Diffusion-based placement migrationHaoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia. 515-520 [doi]
• Is methodology the highway out of verification hell?Francine Bacchini, Gabe Moretti, Harry Foster, Janick Bergeron, Masayuki Nakamura, Shrenik Mehta, Laurent Ducousso. 521-522 [doi]
• Full-chip analysis of leakage power under process variations, including spatial correlationsHongliang Chang, Sachin S. Sapatnekar. 523-528 [doi]
• Variations-aware low-power design with voltage scalingNavid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm. 529-534 [doi]
• Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performanceAshish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director. 535-540 [doi]
• Leakage minimization of nano-scale circuits in the presence of systematic and random variationsSarvesh Bhardwaj, Sarma B. K. Vrudhula. 541-546 [doi]
• A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3)Pascal Urard, L. Paumier, P. Georgelin, T. Michel, V. Lebars, E. Yeo, B. Gupta. 547-548 [doi]
• A design platform for 90-nm leakage reduction techniquesPhilippe Royannez, Hugh Mair, Franck Dahan, Mike Wagner, Mark Streeter, Laurent Bouetel, Joel Blasquez, H. Clasen, G. Semino, Julie Dong, D. Scott, B. Pitts, Claudine Raibaut, Uming Ko. 549-550 [doi]
• A 24 GHz phased-array transmitter in 0.18µm CMOSArun Natarajan, Abbas Komijani, Ali Hajimiri. 551-552 [doi]
• Cache coherence support for non-shared bus architecture on heterogeneous MPSoCsTaeweon Suh, Daehyun Kim, Hsien-Hsin S. Lee. 553-558 [doi]
• A low latency router supporting adaptivity for on-chip interconnectsJongman Kim, Dongkook Park, Theo Theocharides, Narayanan Vijaykrishnan, Chita R. Das. 559-564 [doi]
• Floorplan-aware automated synthesis of bus-based communication architecturesSudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane. 565-570 [doi]
• FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topologyKrishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey. 571-574 [doi]
• Traffic shaping for an FPGA based SDRAM controller with complex QoS requirementsSven Heithecker, Rolf Ernst. 575-578 [doi]
• Microarchitecture-aware floorplanning using a statistical design of experiments approachVidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar. 579-584 [doi]
• Timing-driven placement by grid-warpingZhong Xiu, Rob A. Rutenbar. 585-591 [doi]
• Faster and better global placement by a new transportation algorithmUlrich Brenner, Markus Struzyna. 591-596 [doi]
• Multilevel full-chip routing for the X-based architectureTsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-Jie Chen. 597-602 [doi]
• Matlab extensions for the development, testing and verification of real-time DSP softwareDavid P. Magee. 603-606 [doi]
• Matlab as a development environment for FPGA designTejas M. Bhatt, Dennis McCain. 607-610 [doi]
• Should our power approach be current?Tim Fox, Lou Covey, Susan Mack, David Heacock, Ed P. Huijbregts, Vess Johnson, Avner Kornfeld, Andrew Yang, Paul S. Zuchowski. 611 [doi]
• DTM: dynamic tone mapping for backlight scalingAli Iranli, Massoud Pedram. 612-617 [doi]
• Application/architecture power co-optimization for embedded systems powered by renewable sourcesDexin Li, Pai H. Chou. 618-623 [doi]
• User-perceived latency driven voltage scaling for interactive applicationsLe Yan, Lin Zhong, Niraj K. Jha. 624-627 [doi]
• System-level energy-efficient dynamic task schedulingJianli Zhuo, Chaitali Chakrabarti. 628-631 [doi]
• OPERA: optimization with ellipsoidal uncertainty for robust analog IC designYang Xu, Kan-Lin Hsiung, Xin Li, Ivan Nausieda, Stephen P. Boyd, Lawrence T. Pileggi. 632-637 [doi]
• A unified optimization framework for equalization filter synthesisJihong Ren, Mark R. Greenstreet. 638-643 [doi]
• Template-driven parasitic-aware optimization of analog integrated circuit layoutsSambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi. 644-647 [doi]
• Multi-level approach for integrated spiral inductor optimizationArthur Nieuwoudt, Yehia Massoud. 648-651 [doi]
• Statistical static timing analysis: how simple can we get?Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail. 652-657 [doi]
• Mapping statistical process variations toward circuit performance variability: an analytical modeling approachYu Cao, Lawrence T. Clark. 658-663 [doi]
• Power grid simulation via efficient sampling-based sensitivity analysis and hierarchical symbolic relaxationPeng Li. 664-669 [doi]
• Formal verification: is it real enough?Yaron Wolfsthal, Rebecca M. Gott. 670-671 [doi]
• Can we really do without the support of formal methods in the verification of large designs?Umberto Rossi. 672-673 [doi]
• Streamline verification process with formal property verification to meet highly compressed design cycleProsenjit Chatterjee. 674-677 [doi]
• TCAM enabled on-chip logic minimizationSeraj Ahmad, Rabi N. Mahapatra. 678-683 [doi]
• Hardware speech recognition for user interfaces in low cost, low power devicesSergiu Nedevschi, Rabin K. Patra, Eric A. Brewer. 684-689 [doi]
• Improving java virtual machine reliability for memory-constrained embedded systemsGuangyu Chen, Mahmut T. Kandemir. 690-695 [doi]
• Frequency-based code placement for embedded multiprocessorsCorey Goldfeder. 696-699 [doi]
• Power emulation: a new paradigm for power estimationJoel Coburn, Srivaths Ravi, Anand Raghunathan. 700-705 [doi]
• Implementing low-power configurable processors: practical options and tradeoffsJohn Wei, Chris Rowen. 706-711 [doi]
• Low power network processor design using clock gatingYan Luo, Jia Yu, Jun Yang, Laxmi N. Bhuyan. 712-715 [doi]
• A variation tolerant subthreshold design approachNikhil Jayakumar, Sunil P. Khatri. 716-719 [doi]
• Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reductionYan Lin, Lei He. 720-725 [doi]
• Logic block clustering of large designs for channel-width constrained FPGAsMarvin Tom, Guy G. Lemieux. 726-731 [doi]
• Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibilityAntonio Carlos Schneider Beck, Luigi Carro. 732-737 [doi]
• Beyond safety: customized SAT-based model checkingMalay K. Ganai, Aarti Gupta, Pranav Ashar. 738-743 [doi]
• Efficient SAT solving: beyond supercubesDomagoj Babic, Jesse D. Bingham, Alan J. Hu. 744-749 [doi]
• Prime clauses for fast enumeration of satisfying assignments to boolean circuitsHoonSang Jin, Fabio Somenzi. 750-753 [doi]
• Dynamic abstraction using SAT-based BMCLiang Zhang, Mukul R. Prasad, Michael S. Hsiao, Thomas Sidle. 754-757 [doi]
• BEOL variability and impact on RC extractionN. S. Nagaraj, Tom Bonifield, Abha Singh, Clive Bittlestone, Usha Narasimha, Viet Le, Anthony M. Hill. 758-759 [doi]
• An effective DFM strategy requires accurate process and IP pre-characterizationCarlo Guardiani, Massimo Bertoletti, Nicola Dragone, Marco Malcotti, Patrick McNamara. 760-761 [doi]
• Variation-tolerant circuits: circuit solutions and techniquesJames Tschanz, Keith A. Bowman, Vivek De. 762-763 [doi]
• On the need for statistical timing analysisFarid N. Najm. 764-765 [doi]
• CAD tools for variation toleranceDavid Blaauw, Kaviraj Chopra. 766 [doi]
• Are there economic benefits in DFM?Matt Nowak, Riko Radojcic. 767-768 [doi]
• A generic micro-architectural test plan approach for microprocessor verificationAllon Adir, Hezi Azatchi, Eyal Bin, Ofer Peled, Kirill Shoikhet. 769-774 [doi]
• IODINE: a tool to automatically infer dynamic invariants for hardware designsSudheendra Hangal, Naveen Chandra, Sridhar Narayanan, Sandeep Chakravorty. 775-778 [doi]
• VLIW: a case study of parallelism verificationAllon Adir, Yaron Arbetman, Bella Dubrov, Yossi Lichtenstein, Michal Rimon, Michael Vinov, Massimo A. Calligaro, Andrew Cofler, Gabriel Duffy. 779-782 [doi]
• StressTest: an automatic approach to test generation via activity monitorsIlya Wagner, Valeria Bertacco, Todd M. Austin. 783-788 [doi]
• Smart diagnostics for configurable processor verificationSadik Ezer, Scott Johnson. 789-794 [doi]
• Power-aware placementYongseok Cheon, Pei-Hsin Ho, Andrew B. Kahng, Sherief Reda, Qinke Wang. 795-800 [doi]
• How accurately can we model timing in a placement engine?Amit Chowdhary, Karthik Rajagopal, Satish Venkatesan, Tung Cao, Vladimir Tiourin, Yegna Parasuram, Bill Halpin. 801-806 [doi]
• Efficient and accurate gate sizing with piecewise convex delay modelsHiran Tennakoon, Carl Sechen. 807-812 [doi]
• Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid methodYuantao Peng, Xun Liu. 813-818 [doi]
• Minimising buffer requirements of synchronous dataflow graphs with model checkingMarc Geilen, Twan Basten, Sander Stuijk. 819-824 [doi]
• Unified high-level synthesis and module placement for defect-tolerant microfluidic biochipsFei Su, Krishnendu Chakrabarty. 825-830 [doi]
• Towards scalable flow and context sensitive pointer analysisJianwen Zhu. 831-836 [doi]
• MiniBit: bit-width optimization via affine arithmeticDong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk. 837-840 [doi]
• A non-parametric approach for dynamic range estimation of nonlinear systemsBin Wu, Jianwen Zhu, Farid N. Najm. 841-844 [doi]
• Path delay test compaction with process variation toleranceSeiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato. 845-850 [doi]
• A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACsRasit Onur Topaloglu, Alex Orailoglu. 851-856 [doi]
• Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologiesLuigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian. 857-862 [doi]
• Asynchronous circuits transient faults sensitivity evaluationYannick Monnet, Marc Renaudin, Régis Leveugle. 863-868 [doi]
• Deterministic approaches to analog performance space exploration (PSE)Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann. 869-874 [doi]
• Mixed signal design space exploration through analog platformsFernando De Bernardinis, Pierluigi Nuzzo, Alberto L. Sangiovanni-Vincentelli. 875-880 [doi]
• Performance space modeling for hierarchical synthesis of analog integrated circuitsGeorges G. E. Gielen, Trent McConaghy, Tom Eeckelaert. 881-886 [doi]
• Structured/platform ASIC apprentices: which platform will survive your board room?Ron Wilson, Joe Gianelli, Chris Hamlin, Ken McElvain, Steve Leibson, Ivo Bolson, Rich Tobias, Raul Camposano. 887-888 [doi]
• Quasi-static assignment of voltages and optional cycles for maximizing rewards in real-time systems with energy c-onstraintsLuis Alejandro Cortés, Petru Eles, Zebo Peng. 889-894 [doi]
• DC-DC converter-aware power management for battery-operated embedded systemsYongseok Choi, Naehyuck Chang, Taewhan Kim. 895-900 [doi]
• Energy optimal speed control of devices with discrete speed setsRavishankar Rao, Sarma B. K. Vrudhula. 901-904 [doi]
• Optimal procrastinating voltage scheduling for hard real-time systemsYan Zhang, Zhijian Lu, John Lach, Kevin Skadron, Mircea R. Stan. 905-908 [doi]
• Flexible ASIC: shared masking for multiple media processorsJennifer L. Wong, Farinaz Koushanfar, Miodrag Potkonjak. 909-914 [doi]
• Device and architecture co-optimization for FPGA power reductionLerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He. 915-920 [doi]
• Exploring technology alternatives for nano-scale FPGA interconnectsAman Gayasen, Narayanan Vijaykrishnan, Mary Jane Irwin. 921-926 [doi]
• Piece-wise approximations of RLCK circuit responses using moment matchingChirayu S. Amin, Yehea I. Ismail, Florentin Dartu. 927-932 [doi]
• A quasi-convex optimization approach to parameterized model order reductionKin Cheong Sou, Alexandre Megretski, Luca Daniel. 933-938 [doi]
• Structure preserving reduction of frequency-dependent interconnectQuming Zhou, Kartik Mohanram, Athanasios C. Antoulas. 939-942 [doi]
• Segregation by primary phase factors: a full-wave algorithm for model order reductionThomas J. Klemas, Luca Daniel, Jacob K. White. 943-946 [doi]