Abstract is missing.
- Binning for IC Quality: Experimental Studies on the SEMATECH DataAdit D. Singh, David R. Lakin II, Gaurav Sinha, Phil Nigh. 4-10 [doi]
- A Yield Improvement Program Using Process Control and Process Optimization for Particle Reduction Using In Situ Particle Monitoring on a Semitool MagnumLeon J. P. Vogels, M. W. C. Dohmen, P. Van Duijvenboden, Robert A. Latimer, J. D. O. Heffernan. 11-16 [doi]
- Management of Critical Areas and Defectivity Data for Yield Trend ModelingSandrine Barberan, Frederic Duvivier. 17 [doi]
- Yield and Routing Objectives in FloorplanningIsrael Koren, Zahava Koren. 28-36 [doi]
- Orphan Metal Removal as an Element of DFMNeil Harrison. 37-43 [doi]
- A Comparison of Efficient Dot Throwing and Shape Shifting Extra Material Critical Area EstimationGerard A. Allan. 44 [doi]
- A Fast Minimum Layout Perturbation Algorithm for Electromigration Reliability EnhancementZhan Chen, Fook-Luen Heng. 56-63 [doi]
- FPGA Design for Decimeter Scale Integration (DMSI)Glenn H. Chapman. 64-72 [doi]
- Process Variations and their Impact on Circuit OperationSuriyaprakash Natarajan, Melvin A. Breuer, Sandeep K. Gupta. 73 [doi]
- Comprehensive Defect Analysis and Defect Coverage of CMOS CircuitsDhamin Al-Khalili, Saman Adham, Come Rozon, Moazzem Hossain, D. Racz. 84-92 [doi]
- Characterization of CMOS Defects using Transient Signal AnalysisJames F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan. 93-101 [doi]
- Accurate Fault Modeling and Fault Simulation of Resistive BridgesVijay R. Sar-Dessai, D. M. H. Walker. 102-107 [doi]
- Functional Verification Coverage vs. Physical Stuck-at Fault CoverageXiao Sun, Carmie Hull. 108-116 [doi]
- An Integrated HW and SW Fault Injection Environment for Real-Time SystemsAlfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda, Pierluigi Civera. 117 [doi]
- Increasing Current Testing ResolutionClaude Thibeault. 126-134 [doi]
- On-Chip Test Embedding for Multi-Weighted Random LFSRsDimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar. 135 [doi]
- A New Method for Testing EEPLA sAvinash Munshi, Fred J. Meyer, Fabrizio Lombardi. 146-154 [doi]
- C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and ApplicationsTh. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas. 155-163 [doi]
- On the Complexity of Sequential Testing in Configurable FPGAsWenyi Feng, Fred J. Meyer, Wei-Kang Huang, Fabrizio Lombardi. 164 [doi]
- Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional BlocksCecilia Metra, Michele Favalli, Bruno Riccò. 174-182 [doi]
- Systematic AUED Codes for Self-Checking ArchitecturesDonatella Sciuto, Cristina Silvano, Renato Stefanelli. 183-191 [doi]
- Challenges of Built-In Current Sensor DesignsYu-Yau Guo, Jien-Chung Lo. 192 [doi]
- On the Current Behavior of Faulty and Fault-Free ICs and the Impact on DiagnosisClaude Thibeault, Luc Boisvert. 202-210 [doi]
- A Systematic Approach for Diagnosing Multiple Delay FaultsJayabrata Ghosh-Dastidar, Nur A. Touba. 211-216 [doi]
- Diagnosis of Scan Chain FailuresYuejian Wu. 217 [doi]
- Error-Correcting Goldschmidt Dividers Using Time Shared TMRW. Lynn Gallagher, Earl E. Swartzlander Jr.. 224-232 [doi]
- Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-Based SystemsSergio D Angelo, Cecilia Metra, Sandro Pastore, A. Pogutz, Giacomo R. Sechi. 233-240 [doi]
- Reducing Fault Sensitivity of Microprocessor-Based Systems by Modifying Workload StructureDaniel Audet, Steve Masson, Yvon Savaria. 241 [doi]
- Transient and Intermittent Fault Recovery without RollbackSamuel Norman Hamilton, Alex Orailoglu. 252-260 [doi]
- Highly Reliable Systems with Differential Built-In Current SensorsJien-Chung Lo. 261-269 [doi]
- A Silicon Compiler for Fault-Tolerant ROMsAnurag Gupta, Kanad Chakraborty, Pinaki Mazumder. 270-275 [doi]
- Self-Reconfiguration Scheme of 3D-Mesh ArraysSusumu Horiguchi, Issei Numata. 276 [doi]
- A System for Evaluating On-Line Testability at the RT-levelSilvia Chiusano, Fulvio Corno, Matteo Sonza Reorda, Roberto Vietti. 284-291 [doi]
- High-level Synthesis of Data Paths with Concurrent Error DetectionAnna Antola, Vincenzo Piuri, Mariagiovanna Sami. 292-300 [doi]
- Graceful Degradation in Synthesis of VLSI ICsAlex Orailoglu. 301-311 [doi]
- Designing for Yield: A Defect-Tolerant Approach to High-Level SynthesisMarco Broglia, Giacomo Buonanno, Mariagiovanna Sami, M. Selvini. 312-317 [doi]
- High-Level BIST Synthesis for Delay TestingXiaowei Li, Paul Y. S. Cheung. 318 [doi]
- Yield Enhancement by Multi-level Linear Modeling of Non-Idealities in an Interpolated Flash ADCsAndrea Boni, Andrea Pierazzi. 326-334 [doi]
- Specification-Driven Test Design for Analog CircuitsPramodchandran N. Variyam, Abhijit Chatterjee. 335-340 [doi]
- Modular Fault Simulation of Mixed Signal Circuits with Fault Ranking by SeverityAlfred V. Gomes, Ramakrishna Voorakaranam, Abhijit Chatterjee. 341-348 [doi]
- BIST Module for Mixed-Signal CircuitsSerge N. Demidenko, Vincenzo Piuri, Vyacheslav N. Yarmolik, A. Shmidman. 349 [doi]