Table of Contents

• Design Without BordersJan M. Rabaey. 3 [doi]
• Semiconductor and EDA Challenges: Still Lots To Solve!Chi-Foon Chan. 4 [doi]
• Short Distance Wireless, Dense Networks, and Their OpportunitiesJan M. Rabaey, Yuen-Hui Chee, David Chen, Luca De Nardis, Simone Gambini, Davide Guermandi, Michael Mark, Nathan Pletcher. 7 [doi]
• Error-Aware DesignFadi J. Kurdahi, Ahmed M. Eltawil, Amin Khajeh Djahromi, Mohammad A. Makhzan, Stanley Cheng. 8-15 [doi]
• Ulta-Low-Power Wireless Sensor Node Design on 100 uW Scavenging Energy for Applications In Biomedical MonitoringMladen Berekovic. 16-18 [doi]
• An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic ModelsMohammad Mirza-Aghatabar, Somayyeh Koohi, Shaahin Hessabi, Massoud Pedram. 19-26 [doi]
• Streaming consistency: a model for efficient MPSoC designJan Willem van den Brand, Marco Bekooij. 27-34 [doi]
• A FPGA Optimised Digital Real-Time Mutichannel Correlator ArchitectureChristian Jakob, A. Th. Schwarzbacher, Bernhard Hoppe, R. Peters. 35-42 [doi]
• Design and Implementation of a 50MHZ DXT CoProcessorMohammad Amin Amiri, Reza Ebrahimi Atani, Sattar Mirzakuchaki, Mojdeh Mahdavi. 43-50 [doi]
• A resource optimized Processor Core for FPGA based SoCsGerald Hempel, Christian Hochberger. 51-58 [doi]
• Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java MicroarchitectureMartin Zabel, Thomas B. Preuber, Peter Reichel, Rainer G. Spallek. 59-62 [doi]
• Decoupling of Computation and Communication with a Communication AssistArno Moonen, Marco Bekooij, Rene van den Berg, Jef L. van Meerbergen. 63-68 [doi]
• An Implementation of an Address Generator Using Hash MemoriesTsutomu Sasao, Munehiro Matsuura. 69-76 [doi]
• Experiences with a FPGA-based Reed/Solomon Encoding CoprocessorVolker Hampel, Peter Sobe, Erik Maehle. 77-84 [doi]
• Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS SubtractionPanagiotis D. Vouzis, Sylvain Collange, Mark G. Arnold. 85-93 [doi]
• General Digit-Serial Normal Basis Multiplier with Distributed OverlapMartin Novotný, Jan Schmidt. 94-101 [doi]
• An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error DetectorEmanuele Sciagura, Paolo Zicari, Stefania Perri, Pasquale Corsonello. 102-108 [doi]
• A Robust GF(p) Parallel Arithmetic Unit for Public Key CryptographySantosh Ghosh, Monjur Alam, Indranil Sengupta, Dipanwita Roy Chowdhury. 109-115 [doi]
• A Hardware/Software Co-design vs. Hardware Implementation of the Modular Exponentiation Using the Sliding-Window Method with Constant-Length PartitioningNadia Nedjah, Luiza de Macedo Mourelle. 116-123 [doi]
• Fault Handling in FPGAs and Microcontrollers in Safety-Critical Embedded Applications: A Comparative SurveyFalk Salewski, Adam Taylor. 124-131 [doi]
• Exploiting Parallelism in Double Path Adders Structure for Increased Throughput of Floating Point AdditionAlexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo. 132-137 [doi]
• Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate ArraysScott Miller, Mihai Sima, Michael McGuire. 138-146 [doi]
• A Run-Time Scheduling Framework for a Reconfigurable Hardware EmulatorRene Beckert, Thomas Fuchs, Steffen Rülke, Wolfram Hardt. 147-150 [doi]
• A Serial Logarithmic Number System ALUMark G. Arnold, Panagiotis D. Vouzis. 151-156 [doi]
• Functional Test-Case Generation by a Control Transaction Graph for TLM VerificationMohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi. 157-164 [doi]
• An Embedded Implementation of the Microsoft Common Language InfrastructureJoseph C. Libby, Kenneth B. Kent. 165-172 [doi]
• Evaluating the Model Accuracy in Automated Design Space ExplorationKalle Holma, Mikko Setälä, Erno Salminen, Timo D. Hämäläinen. 173-180 [doi]
• P-Ware: A precise and scalable component-based simulation tool for embedded multiprocessor industrial applicationsIsmail Assayad, Sergio Yovine. 181-188 [doi]
• Latency Minimization for Synchronous Data Flow GraphsAmir Hossein Ghamarian, Sander Stuijk, Twan Basten, Marc Geilen, Bart D. Theelen. 189-196 [doi]
• On Complexity of Internal and External Equivalence CheckingEugene Goldberg, Kanupriya Gulati. 197-206 [doi]
• The Criteria of Functional Delay Test Quality AssessmentEduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas. 207-214 [doi]
• RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-ChipGuillermo Payá Vayá, Javier Martín-Langerwerf, Peter Pirsch. 215-221 [doi]
• Functional Verification of RTL Designs driven by Mutation Testing metricsYoussef Serrestou, Vincent Beroulle, Chantal Robach. 222-227 [doi]
• Execution-time Prediction for Dynamic Streaming Applications with Task-level ParallelismPeter Poplavko, Twan Basten, Jef L. van Meerbergen. 228-235 [doi]
• A New Framework for Design and Simulation of Complex Hardware/Software SystemsCarlo Brandolese, D. Crespi, Laura Frigerio, Fabio Salice. 236-243 [doi]
• A DRAM Precharge Policy Based on Address AnalysisChiyuan Ma, Shuming Chen. 244-248 [doi]
• High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM ProcessMinh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis. 249-256 [doi]
• Controller Design and Verification for A Pipeline Image Processor based on An Extended Petri netKatsumi Wasaki, Toshiaki Harai, Tamotsu Hayashi, Ken-ichi Arai. 257-260 [doi]
• Power Estimation of Time Variant SoCs with TAPESAndreas Lankes, Thomas Wild, Johannes Zeppenfeld. 261-264 [doi]
• Component-Based Hardware/Software Co-SimulationPing Hang Cheung, Kecheng Hao, Fei Xie. 265-270 [doi]
• Toggle Equivalence Preserving (TEP) Logic OptimizationEugene Goldberg, Kanupriya Gulati, Sunil P. Khatri. 271-279 [doi]
• Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA ImplementationShinobu Nagayama, Tsutomu Sasao, Jon T. Butler. 280-287 [doi]
• Graph Matching Constraints for Synthesis with Complex ComponentsAna Fuentes Martinez, Krzysztof Kuchcinski. 288-295 [doi]
• OOCE: Object-Oriented Communication Engine for SoC DesignJesús Barba, Fernando Rincón, Francisco Moya, Felix Jesús Villanueva, David Villa, Julio Dondo, Juan Carlos López. 296-302 [doi]
• Timing- / Power-Optimization for Digital Logic Based on Standard CellsHeinrich Theodor Vierhaus, Helmut Rossmann, Silvio Misera. 303-306 [doi]
• Energy Based Design Space Exploration of Multiprocessor VLIW ArchitecturesManoj Gupta, Mayank Gupta, Neeraj Goel, M. Balaksrishnan. 307-310 [doi]
• Reducing the Overhead of Real-Time Operating System through Reconfigurable HardwareMoonvin Song, Sang Hoon Hong, Yunmo Chung. 311-316 [doi]
• Silicon Compaction/Defragmentation for Partial Runtime ReconfigurationKolin Paul, Joel Porquet, Josep Llosa. 317-324 [doi]
• A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI InterconnectsJ. V. R. Ravindra, M. B. Srinivas. 325-330 [doi]
• A New Class of Cellular AutomataHosna Jabbari, Jon C. Muzio, Lin Sun. 331-338 [doi]
• Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic SynthesisMehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi. 339-346 [doi]
• Analysis of Variable Reordering on the QMDD Representation of Quantum CircuitsSharon Van Schaick, Kenneth B. Kent. 347-352 [doi]
• Merge Logic for Clustered Multithreaded VLIW ProcessorsManoj Gupta, Fermín Sánchez, Josep Llosa. 353-360 [doi]
• Automatic Generation of Low-Complexity FFT/IFFT Cores for Multi-Band OFDM SystemsNicola E. L Insalata, Sergio Saponara, Luca Fanucci, Pierangelo Terreni. 361-368 [doi]
• Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC CodesGiuseppe Gentile, Massimo Rovini, Luca Fanucci. 369-375 [doi]
• FPGA/DSP-based Configurable Multi-Channel CounterD. Audino, F. Baronti, A. Lazzeri, Roberto Roncella, Roberto Saletti. 376-382 [doi]
• Design and Implementation of a 90nm Low bit-rate Image Compression CorePasquale Corsonello, Stefania Perri, G. Staino, Marco Lanuzza, Giuseppe Cocorullo. 383-389 [doi]
• FATTY: A Reliable FAT File SystemAlei Liang, Kejia Liu, Xiaoyong Li, Haibing Guan. 390-395 [doi]
• Proving Completeness of Properties in Formal Verification of Counting Heads for RailwaysSebastian Kinder, Rolf Drechsler. 396-403 [doi]
• Architecture Exploration of 3D Video Recorder Using Virtual Platform ModelsMatti Eteläperä, Janne Vatjus Anttila, Juha Pekka Soinimen. 404-411 [doi]
• FPGA-based Road Traffic VideodetectorMarek Gorgon, Piotr Pawlik, Miroslaw Jablonski, Jaromir Przybylo. 412-419 [doi]
• Safety and Security-driven Design of Networked Embedded SystemsMiroslav Svéda, Roman Trchalik. 420-423 [doi]
• MPSoC memory optimization for digital camera applicationsYoucef Bouchebaba, Bruno Lavigueur, Bruno Girodias, Gabriela Nicolescu, Pierre G. Paulin. 424-427 [doi]
• Architecture of a Small Low-Cost SatelliteDante Del Corso, Claudio Passerone, Leonardo Maria Reyneri, Claudio Sansoè, Marco Borri, Stefano Speretta, Maurizio Tranchero. 428-431 [doi]
• FPGA Accelerating Algorithms of Active Shape Model in People Tracking ApplicationsJinbo Xu, Yong Dou, Junfeng Li, Xingming Zhou, Qiang Dou. 432-435 [doi]
• A Sliced Coprocessor for Native Clifford Algebra OperationsS. Franchini, Antonio Gentile, M. Grimaudo, C. A. Hung, Sandro Impastato, Filippo Sorbello, Giorgio Vassallo, Salvatore Vitabile. 436-439 [doi]
• A Hardware-Software Platform for Design and Verification of In-Motorcycle Electronic SystemsF. Baronti, F. Lenzi, Roberto Roncella, Roberto Saletti. 440-443 [doi]
• An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion EstimationSerkan Oktem, Ilker Hamzaoglu. 444-447 [doi]
• An Efficient Intra Prediction Hardware Architecture for H.264 Video DecodingEsra Sahin, Ilker Hamzaoglu. 448-454 [doi]
• Evaluating Energy Consumption in Wireless Sensor Networks ApplicationsAgustin Barberis, Leonardo Barboni, Maurizio Valle. 455-462 [doi]
• Simulation Based Verification of Energy Storage Architectures for Higher Class Tags supported by Energy Harvesting DevicesAlex Janek, Christoph Trummer, Christian Steger, Reinhold Weiss, Josef Preishuber-Pfluegl, Markus Pistauer. 463-462 [doi]
• Adaptive Distance Estimation and Localization in WSN using RSSI MeasuresAbdalkarim Awad, Thorsten Frunzke, Falko Dressler. 471-478 [doi]
• A Proposal of New Join Operators for Sensor Network DatabasesSeungjae Lee, Changhwa Kim, Sangkyung Kim. 479-484 [doi]
• A Wireless Sensor Node Architecture Using Remote Power Charging, for Interaction ApplicationsMatthew D Souza, Konstanty Bialkowski, Adam Postula, Montserrat Ros. 485-494 [doi]
• GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-MultiprocessorsChristoph Puttmann, Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert. 495-502 [doi]
• On network-on-chip comparisonErno Salminen, Ari Kulmala, Timo D. Hämäläinen. 503-510 [doi]
• Increasing NoC Performance and Utilisation using a Dual Packet Exit StrategyMikael Millberg, Axel Jantsch. 511-518 [doi]
• Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layerD. Mangano, G. Falconeri, C. Pistritto, A. Scandurra. 519-526 [doi]
• Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip ArchitecturesTimo Schönwald, Jochen Zimmermann, Oliver Bringmann, Wolfgang Rosenstiel. 527-534 [doi]
• On-Chip Verification of NoCs Using Assertion ProcessorsMohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi. 535-538 [doi]
• Security Aspects in Networks-on-Chips: Overview and Proposals for Secure ImplementationsLeandro Fiorin, Cristina Silvano, Mariagiovanna Sami. 539-542 [doi]
• NoC Topologies Exploration based on Mapping and Simulation ModelsLuciano Bononi, Nicola Concer, Miltos D. Grammatikakis, Marcello Coppola, Riccardo Locatelli. 543-546 [doi]
• Application-Specific Topology Design Customization for STNoCGianluca Palermo, Cristina Silvano, Giovanni Mariani, Riccardo Locatelli, Marcello Coppola. 547-550 [doi]
• Novel Agent-Based Management for Fault-Tolerance in Network-on-ChipPekka Rantala, Jouni Isoaho, Hannu Tenhunen. 551-555 [doi]
• On the impact of serialization on the cache performances in Network-on-Chip based MPSoCsPaolo Meloni, Giovanni Busonera, Salvatore Carta, Luigi Raffo. 556-562 [doi]
• On the Construction of Small Fully Testable Circuits with Low DepthGörschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler. 563-569 [doi]
• On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale TechnologyDavid Roberts, Nam Sung Kim, Trevor N. Mudge. 570-578 [doi]
• Concurrent Error Detection for FSMs Designed for Implementation with Embedded Memory Blocks of FPGAsAndrzej Krasniewski. 579-586 [doi]
• Fault Injection Techniques and their Accelerated Simulation in SystemCSilvio Misera, Heinrich Theodor Vierhaus, André Sieber. 587-595 [doi]
• Hybrid BIST Optimization Using Reseeding and Test Set CompactionGert Jervan, Elmet Orasson, Helena Kruus, Raimund Ubar. 596-603 [doi]
• Fault Diagnosis in Integrated Circuits with BISTRaimund Ubar, Sergei Kostin, Jaan Raik, Teet Evartson, Harri Lensen. 604-610 [doi]
• Testability Analysis Based on the Identification of Testable Blocks with Predefined PropertiesJaroslav Skarvada, Tomas Herrman, Zdenek Kotásek. 611-618 [doi]
• An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS CircuitsElham K. Moghaddam, Shaahin Hessabi. 619-625 [doi]
• Test Controller Synthesis Constrained by Circuit Testability AnalysisRichard Ruzicka, Josef Strnadel. 626-633 [doi]
• Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance AssessmentOana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai. 634-640 [doi]
• Scaling Analytical Models for Soft Error Rate Estimation Under a Multiple-Fault EnvironmentChristian J. Hescott, Drew C. Ness, David J. Lilja. 641-648 [doi]
• A Low Power Information Redundant Concurrent Error Detecting Asynchronous ProcessorM. Marshall, G. Russell. 649-656 [doi]
• Pseudo-Random Pattern Generator Design for Column-Matching BISTPetr Fiser. 657-663 [doi]
• An Efficient BIST Scheme for Non-Restoring Array DividersHaridimos T. Vergos. 664-667 [doi]
• Hierarchical Identification of Untestable Faults in Sequential CircuitsJaan Raik, Raimund Ubar, Anna Krivenko, Margus Kruus. 668-671 [doi]
• The importance of At-Speed Scan Testing: an industrial experienceF. Baronti, Roberto Roncella, Roberto Saletti, P. D Abramo, L. Di Piro, H. Fabian, M. Giardi. 672-675 [doi]
• Online Protocol Testing for FPGA Based Fault Tolerant SystemsJiri Tobola, Zdenek Kotásek, Jan Korenek, Tomás Martínek, Martin Straka. 676-679 [doi]
• Performance Evaluation of Instruction Set Extensions for Long Integer Modular Arithmetic on a SPARC V8 ProcessorJohann Großschädl, Stefan Tillich, Alexander Szekely. 680-689 [doi]