Table of Contents

• Sampling from the Multivariate Gaussian Distribution using Reconfigurable HardwareDavid B. Thomas, Wayne Luk. 3-12 [doi]
• A Fast FPGA-Based 2-Opt Solver for Small-Scale Euclidean Traveling Salesman ProblemIoannis Mavroidis, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos. 13-22 [doi]
• On the Acceleration of Shortest Path Calculations in Transportation NetworksZachary K. Baker, Maya Gokhale. 23-34 [doi]
• Enhancing Relocatability of Partial Bitstreams for Run-Time ReconfigurationTobias Becker, Wayne Luk, Peter Y. K. Cheung. 35-44 [doi]
• A Library and Platform for FPGA Bitstream ManipulationAdam Megacz. 45-54 [doi]
• A Structural Object Programming Model, Architecture, Chip and Tools for Reconfigurable ComputingMichael Butts, Anthony Mark Jones, Paul Wasson. 55-64 [doi]
• Configurable Transactional MemoryChristoforos Kachris, Chidamber Kulkarni. 65-72 [doi]
• A Reconfigurable Hardware Interface for a Modern Computing SystemPhilip Garcia, Katherine Compton. 73-84 [doi]
• FPGA Acceleration of Gene Rearrangement AnalysisJason D. Bakos. 85-94 [doi]
• FPGA-accelerated seed generation in Mercury BLASTPArpith C. Jacob, Joseph M. Lancaster, Jeremy Buhler, Roger D. Chamberlain. 95-106 [doi]
• Systolic Architecture for Computational Fluid Dynamics on FPGAsKentaro Sano, Takanori Iizuka, Satoru Yamamoto. 107-116 [doi]
• FPGA-Based Multigrid Computation for Molecular Dynamics SimulationsYongfeng Gu, Martin C. Herbordt. 117-126 [doi]
• Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale ComputingRon Sass, William V. Kritikos, Andrew G. Schmidt, Srinivas Beeravolu, Parag Beeraka. 127-140 [doi]
• Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAsChristos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung. 141-150 [doi]
• K-means Clustering for Multispectral Images Using Floating-Point DivideXiaojun Wang, Miriam Leeser. 151-162 [doi]
• Optimizing Logarithmic Arithmetic on FPGAsHaohuan Fu, Oskar Mencer, Wayne Luk. 163-172 [doi]
• Generating FPGA-Accelerated DFT LibrariesPaolo D Alberto, Peter A. Milder, Aliaksei Sandryhaila, Franz Franchetti, James C. Hoe, José M. F. Moura, Markus Püschel, Jeremy R. Johnson. 173-184 [doi]
• An FPGA implementation of pipelined multiplicative division with IEEE RoundingRonen Goldberg, Guy Even, Peter-Michael Seidel. 185-196 [doi]
• Integer Factorization Based on Elliptic Curve Method: Towards Better Exploitation of Reconfigurable HardwareGiacomo de Meulenaer, François Gosset, Guerric Meurice de Dormale, Jean-Jacques Quisquater. 197-206 [doi]
• Matched Filter Computation on FPGA, Cell and GPUZachary K. Baker, Maya B. Gokhale, Justin L. Tripp. 207-218 [doi]
• A Data-Driven Approach for Pipelining Sequences of Data-Dependent LoopsRui Rodrigues, João M. P. Cardoso, Pedro C. Diniz. 219-228 [doi]
• Writing Portable Applications that Dynamically Bind at Run Time to Reconfigurable HardwareNicholas Moore, Albert Conti, Miriam Leeser, Laurie A. Smith King. 229-238 [doi]
• Mitrion-C Application Development on SGI Altix 350/RC100Volodymyr V. Kindratenko, Robert J. Brunner, Adam D. Myers. 239-250 [doi]
• Automatic On-chip Memory Minimization for Data ReuseQiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung. 251-260 [doi]
• Scientific Application Acceleration with Reconfigurable Functional UnitsKyle Rupnow, Keith D. Underwood, Katherine Compton. 261-274 [doi]
• Design and Implementation of a Highly Parameterised FPGA-Based Skeleton for Pairwise Biological Sequence AlignmentKhaled Benkrid, Ying Liu, Abdsamad Benkrid. 275-278 [doi]
• The Case for Dynamic Execution on Dynamic HardwareCharles Ross, Wim Böhm. 279-280 [doi]
• On Solving RC5 Challenges with FPGAsGuerric Meurice de Dormale, John Bass, Jean-Jacques Quisquater. 281-282 [doi]
• Operating System Integration and Performance of a Multi Stream Cipher Architecture for Reconfigurable System-on-ChipChin Mun Wee, Peter R. Sutton, Neil W. Bergmann. 283-284 [doi]
• A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable LogicHiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi. 285-286 [doi]
• New Protection Mechanisms for Intellectual Property in Reconfigurable LogicTim Güneysu, Bodo Möller, Christof Paar. 287-288 [doi]
• Establishing Chain of Trust in Reconfigurable HardwareThomas Eisenbarth, Tim Güneysu, Christof Paar, Ahmad-Reza Sadeghi, Marko Wolf, Russell Tessier. 289-290 [doi]
• Hand-based Interface for Augmented RealityF. Javier Toledo-Moreo, J. Javier Martínez-Álvarez, José Manuel Ferrández de Vicente. 291-292 [doi]
• Discrete-Time Cellular Neural Networks in FPGAJ. Javier Martínez-Álvarez, F. Javier Toledo-Moreo, José Manuel Ferrández de Vicente. 293-294 [doi]
• Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCsGilles Sassatelli, Nicolas Saint-Jean, Pascal Benoit, Lionel Torres, Michel Robert, Cristiane R. Woszezenki, Ismael Grehs, Fernando Gehm Moraes. 295-296 [doi]
• Code Compressor and Decompressor for Ultra Large Instruction Width Coarse-Grain Reconfigurable SystemsNazish Aslam, Mark Milward, Ioannis Nousias, Tughrul Arslan, Ahmet T. Erdogan. 297-298 [doi]
• Software/Hardware Co-Scheduling for Reconfigurable Computing SystemsProshanta Saha, Tarek A. El-Ghazawi. 299-300 [doi]
• Mapping Real Time Operating System on Reconfigurable Instruction Cell Based ArchitecturesHan Wei, Mark Muir, Ioannis Nousias, Tughrul Arslan, Ahmet T. Erdogan. 301-304 [doi]
• Abstracting Modern FCCMs To Provide a Single Interface to Architectural ResourcesGraham Schelle, Dirk Grunwald. 305-308 [doi]
• A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable LogicHiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi. 309-310 [doi]
• Heterogeneous Floorplanner for FPGALove Singhal, Elaheh Bozorgzadeh. 311-312 [doi]
• Automatic Self-Reconfiguration of System-on-Chip PeripheralsNeil W. Bergmann, Yi Lu 0004, John A. Williams. 313-316 [doi]
• A Hybrid Memory Sub-system for Video Coding ApplicationsSu-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung. 317-318 [doi]
• Rapid Prototyping of Large-scale Analog Circuits With Field Programmable Analog ArrayI. Faik Baskaya, Brian Gestner, Christopher M. Twigg, Sung Kyu Lim, David V. Anderson, Paul E. Hasler. 319-320 [doi]
• PixelStreams-based implementation of videodetectorMarek Gorgon, Piotr Pawlik, Miroslaw Jablonski, Jaromir Przybylo. 321-322 [doi]
• Design Space Exploration for the BLAST Algorithm ImplementationEuripides Sotiriades, Apostolos Dollas. 323-326 [doi]
• An Integrated Video Compression, Encryption and Information Hiding Architecture based on the SCAN Algorithm and the Stretch TechnologyGrigorios Chrysos, Apostolos Dollas, Nikolaos G. Bourbakis, J. Sukarno Mertoguno. 327-330 [doi]
• A Configurable Processor Synthesis SystemWanda Gay, Clay S. Gloster Jr.. 331-332 [doi]
• Low-Cost Stereo Vision on an FPGAChris Murphy, Daniel Lindquist, Ann Marie Rynning, Thomas Cecil, Sarah Leavitt, Mark L. Chang. 333-334 [doi]
• Methodology and Experimental Setup for the Determination of System-level Dynamic Reconfiguration OverheadKyprianos Papadimitriou, Antonis Anyfantis, Apostolos Dollas. 335-336 [doi]
• Quantifying Effective Memory Bandwidth of Platform FPGAsAndrew G. Schmidt, Ron Sass. 337-338 [doi]
• A Flexible Filter Processor for Fading Channel SimulationAmirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel. 339-342 [doi]
• RBoot: Software Infrastructure for a Remote FPGA LaboratoryKushal Datta, Ron Sass. 343-344 [doi]
• Jumble: A Hardware-in-the-Loop Simulation System for JHDLDavid Castells-Rufas, Jordi Carrabina. 345-348 [doi]
• Sparse Matrix-Vector Multiplication Design on FPGAsJunqing Sun, Gregory D. Peterson, Olaf O. Storaasli. 349-352 [doi]
• Changing Output Quality for Thermal ManagementPhillip H. Jones, James Moscola, Young H. Cho, John W. Lockwood. 353-354 [doi]
• Hardware/Software co-design of a key point detector on FPGAHarding Djakou Chati, Felix Mühlbauer, Tim Braun, Christophe Bobda, Karsten Berns. 355-356 [doi]