Table of Contents

• A generic execution model for efficient performance evaluation of system architectures at transaction levelSébastien LeNours, Anthony Barreteau, Olivier Pasquier. 1-8 [doi]
• Semi-formal refinement of heterogeneous embedded systems by foreign model integrationSeyed Hosein Attarzadeh Niaki, Ingo Sander. 1-8 [doi]
• Does asynchronous technology bring robustness in synchronous circuit monitoring?Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet, Alejandro Chagoya. 1-6 [doi]
• Abstract modelling and estimation of a high performance Tobey's PGASumit Adhikari, Christoph Grimm, Jan Haase. 1-6 [doi]
• A machine-readable specification of analog circuits for integration into a validation flowMingyu Ma, Lars Hedrich, Christian Sporrer. 1-8 [doi]
• Integrating system descriptions by clocked guarded actionsJens Brandt, Mike Gemunde, Klaus Schneider, Sandeep K. Shukla, Jean-Pierre Talpin. 1-8 [doi]
• Systemc-AMS model of a dynamic large-scale satellite-based AIS-like networkMu Zhou, René van Leuken. 1-8 [doi]
• A case study on message-based discrete event simulation for Transaction Level ModelingBastian Haetzer, Martin Radetzki. 1-8 [doi]
• A framework for the generation from UML/MARTE models of IPXACT HW platform descriptions for multi-level performance estimationFernando Herrera, Eugenio Villar. 1-8 [doi]
• Behavioral modeling of a CMOS video sensor platform using systemc AMS/TLMFabio Cenni, Serge Scotti, Emmanuel Simeu. 1-6 [doi]
• Improvement of Assertion-Based Verification through the generation of proper test sequencesLaurence Pierre, Laila Damri. 1-8 [doi]
• Impact simulation of changes to development processes: An ESL case studyFrank Poppen, Roland Koppe, Kim Grüttner, Axel Hahn. 1-6 [doi]
• ESL power and performance estimation for heterogeneous MPSOCS using SystemCMartin Streubühr, Rafael Rosales, Ralph Hasholzner, Christian Haubelt, Jürgen Teich. 1-8 [doi]
• Analyzing dependability measures at the Electronic System LevelMarc Michael, Daniel Große, Rolf Drechsler. 1-8 [doi]
• VHDL-AMS model of a dual gate graphene FETIme J. Umoh, Tom J. Kazmierski. 1-5 [doi]
• A UML based framework for efficient validation of TLM 2 modelsVaibhav Jain, Anshul Kumar, Preeti Ranjan Panda. 1-8 [doi]
• Efficient implementation and abstraction of systemc data types for fast simulationNicola Bombieri, Franco Fummi, Valerio Guarnieri, Francesco Stefanni, Sara Vinco. 1-7 [doi]
• Integrated model-based approach and test framework for embedded systemsPadma Iyenghar, Elke Pulvermueller, Clemens Westerkamp, Juergen Wuebbelmann. 1-8 [doi]
• Designing low-power wireless sensor networksJoseph Wenninger, Javier Moreno, Jan Haase, Christoph Grimm. 1-6 [doi]
• Systemc refinement of abstract adaptive processes for implementation into Dynamically Reconfigurable HardwareFernando Herrera, Eugenio Villar, Philipp A. Hartmann. 1-8 [doi]
• IP-XACT and marte based approach for partially reconfigurable systems-on-chipGilberto Ochoa, El-Bay Bourennane, Ouassila Labbani, Kamel Messaoudi. 1-8 [doi]
• Hardware performance estimation by dynamic schedulingPablo González de Aledo Marugán, Javier Gonzalez Bayon, Pablo Sánchez Espeso. 1-6 [doi]
• Bringing C++ productivity to VHDL world: From language definition to a case studyIvan Shcherbakov, Christian Weis, Norbert Wehn. 1-7 [doi]
• Assertion support in high-level synthesis design flowAurélien Ribon, Bertrand Le Gal, Christophe Jégo, Dominique Dallet. 1-8 [doi]
• Schizophrenia and causality in the context of refined clocksMike Gemunde, Jens Brandt, Klaus Schneider. 1-8 [doi]
• A metamodel and semantics for transaction level modelingRauf Salimi Khaligh, Martin Radetzki. 1-8 [doi]
• Efficient realization of control logic in reversible circuitsSebastian Offermann, Robert Wille, Rolf Drechsler. 1-7 [doi]