Abstract is missing.
- Identifying bottlenecks in manufacturing systems using stochastic criticality analysisJoão Bastos, Bram van der Sanden, Olaf Donk, Jeroen Voeten, Sander Stuijk, Ramon R. H. Schiffelers, Henk Corporaal. 1-8 [doi]
- Rethinking of I/O-automata compositionSarah Chabane, Rabéa Ameur-Boulifa, Mohamed Mezghiche. 1-7 [doi]
- Compositional timing-aware semantics for synchronous programmingJoaquín Aguado, Michael Mendler, Jia Jie Wang, Bruno Bodin, Partha S. Roop. 1-8 [doi]
- Symbolic simulation of dataflow synchronous programs with timersGuillaume Baudart, Timothy Bourke, Marc Pouzet. 1-8 [doi]
- Actor fission transformations for executing dataflow programs on manycoresEssayas Gebrewahid, Zain-ul-Abdin. 1-8 [doi]
- Fault analysis in analog circuits through language manipulation and abstractionEnrico Fraccaroli, Francesco Stefanni, Franco Fummi, Mark Zwolinski. 1-7 [doi]
- Towards consistency checking between HDL and UPF descriptionsArthur Kalsing, Laurent Fesquet, Chouki Aktouf. 1-6 [doi]
- Language and hardware acceleration backend for graph processingAndrey Mokhov, Alessandro de Gennaro, Ghaith Tarawneh, Jonny Wray, Georgy Lukyanov, Sergey Mileiko, Joe Scott, Alex Yakovlev, Andrew Brown. 1-7 [doi]
- Real-time ticks for synchronous programmingReinhard von Hanxleden, Timothy Bourke, Alain Girault. 1-8 [doi]
- Runtime task mapping for lifetime budgeting in many-core systemsLiang Wang, Xiaohang Wang, Ho-Fung Leung, Terrence S. T. Mak. 1-8 [doi]
- Towards early validation of firmware-based power management using virtual prototypes: A constrained random approachVladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler. 1-8 [doi]
- Automatic generation of cycle-accurate Simulink blocks from hdl ipsStefano Centomo, Michele Lora, Antonio Portaluri, Francesco Stefanni, Franco Fummi. 1-8 [doi]
- Asil decomposition using SMTMona Safar. 1-6 [doi]