Table of Contents

• Thoughts on Edge IntelligenceMarilyn Wolf. 1 [doi]
• Automatic Implementation of Secure SiliconSerge Leef. 3 [doi]
• Processing Data Where It Makes Sense in Modern Computing Systems: Enabling In-Memory ComputationOnur Mutlu. 5-6 [doi]
• Innovations in IoT for a Safe, Secure, and Sustainable FutureSwarup Bhunia. 7 [doi]
• LPN-based Device Authentication Using Resistive MemoryMd Tanvir Arafin, Hao-Ting Shen, Mark M. Tehranipoor, Gang Qu. 9-14 [doi]
• Leveraging On-Chip Voltage Regulators Against Fault Injection AttacksAli Vosoughi, Selçuk Köse. 15-20 [doi]
• On the Theoretical Analysis of Memristor based True Random Number GeneratorMesbah Uddin, Md Sakib Hasan, Garrett S. Rose. 21-26 [doi]
• Control-Lock: Securing Processor Cores Against Software-Controlled Hardware TrojansDominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Sascha Kegreiss. 27-32 [doi]
• Lightweight Authenticated Encryption for Network-on-Chip CommunicationsJulian Harttung, Elke Franz, Sadia Moriam, Paul Walther. 33-38 [doi]
• Design of a Low-power and Small-area Approximate Multiplier using First the Approximate and then the Accurate Compression MethodTongxin Yang, Tomoaki Ukezono, Toshinori Sato. 39-44 [doi]
• GraphiDe: A Graph Processing Accelerator leveraging In-DRAM-ComputingShaahin Angizi, Deliang Fan. 45-50 [doi]
• An Efficient Time-based Stochastic Computing Circuitry Employing Neuron-MOSTati Erlina, Yan Chen, Renyuan Zhang, Yasuhiko Nakashima. 51-56 [doi]
• Monolithic 8x8 SiPM with 4-bit Current-Mode Flash ADC with Tunable Dynamic RangeVikas Vinayaka, Sachin P. Namboodiri, Shadden Abdalla, Bryan Kerstetter, Francisco Mata-carlos, Daniel Senda, James Skelly, Angsuman Roy, R. Jacob Baker. 57-62 [doi]
• A Systolic SNN Inference Accelerator and its Co-optimized Software FrameworkShasha Guo, Lei Wang, Shuquan Wang, Yu Deng, Zhijie Yang, Shiming Li, Zhige Xie, Qiang Dou. 63-68 [doi]
• Dynamic Beam Width Tuning for Energy-Efficient Recurrent Neural NetworksDaniele Jahier Pagliari, Francesco Panini, Enrico Macii, Massimo Poncino. 69-74 [doi]
• Efficient Softmax Hardware Architecture for Deep Neural NetworksGaoming Du, Chao Tian, Zhenmin Li, Duoli Zhang, Yong-Sheng Yin, Yiming Ouyang. 75-80 [doi]
• HSIM-DNN: Hardware Simulator for Computation-, Storage- and Power-Efficient Deep Neural NetworksMengshu Sun, Pu Zhao, Yanzhi Wang, Naehyuck Chang, Xue Lin. 81-86 [doi]
• An Area-Efficient Iterative Single-Precision Floating-Point Multiplier Architecture for FPGASunwoong Kim, Rob A. Rutenbar. 87-92 [doi]
• An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits OptimizationZhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Chengyu Hu, Jian Wang, Jinmei Lai. 93-98 [doi]
• Low Voltage Clock Tree Synthesis with Local Gate ClustersCan Sitik, Weicheng Liu, Baris Taskin, Emre Salman. 99-104 [doi]
• TOIC: Timing Obfuscated Integrated CircuitsMahabubul Alam, Swaroop Ghosh, Sujay S. Hosur. 105-110 [doi]
• Design for Eliminating Operation Specific Power Signatures from Digital LogicMd. Badruddoja Majumder, Md Sakib Hasan, Aysha S. Shanta, Mesbah Uddin, Garrett S. Rose. 111-116 [doi]
• Non-Uniform Temperature Distribution in Interconnects and Its Impact on ElectromigrationAli Abbasinasab, Malgorzata Marek-Sadowska. 117-122 [doi]
• Fault Classification and Coverage of Analog Circuits using DC Operating Point and Frequency Response AnalysisSayandeep Sanyal, Shan Pavan Pani Krishna Garapati, Amit Patra, Pallab Dasgupta, Mayukh Bhattacharya. 123-128 [doi]
• Crash Skipping: A Minimal-Cost Framework for Efficient Error Recovery in Approximate Computing EnvironmentsYan Verdeja Herms, Yanjing Li. 129-134 [doi]
• Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOIHao Cai, Menglin Han, Weiwei Shan, Jun Yang, You Wang, Wang Kang, Weisheng Zhao. 135-140 [doi]
• Low Cost Hybrid Spin-CMOS Compressor for Stochastic Neural NetworksBingzhe Li, Jiaxi Hu, M. Hassan Najafi, Steven J. Koester, David J. Lilja. 141-146 [doi]
• Functionally Complete Boolean Logic and Adder Design Based on 2T2R RRAMs for Post-CMOS In-Memory ComputingZongxian Yang, Yixiao Ma, Lan Wei. 147-152 [doi]
• Jump Search: A Fast Technique for the Synthesis of Approximate CircuitsLinus Witschen, Hassan Ghasemzadeh Mohammadi, Matthias Artmann, Marco Platzner. 153-158 [doi]
• SAT-Based Placement Adjustment of FinFETs inside Unroutable Standard Cells Targeting Feasible DRC-Clean RoutingAnton Sorokin, Nikolay Ryzhenko. 159-164 [doi]
• A Scalable and Process Variation Aware NVM-FPGA Placement AlgorithmChengmo Yang, Yuan Xue. 165-170 [doi]
• Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGABo Hu, Jingxiang Tian, Mustafa M. Shihab, Gaurav Rajavendra Reddy, William Swartz, Yiorgos Makris, Benjamin Carrión Schäfer, Carl Sechen. 171-176 [doi]
• HydraRoute: A Novel Approach to Circuit RoutingMohammad Khasawneh, Patrick H. Madden. 177-182 [doi]
• Balanced Factorization and Rewriting Algorithms for Synthesizing Single Flux Quantum Logic CircuitsGhasem Pasandi, Massoud Pedram. 183-188 [doi]
• A Majority Logic Synthesis Framework for Adiabatic Quantum-Flux-Parametron Superconducting CircuitsRuizhe Cai, Olivia Chen, Ao Ren, Ning Liu, Caiwen Ding, Nobuyuki Yoshikawa, Yanzhi Wang. 189-194 [doi]
• A Processing-In-Memory Implementation of SHA-3 Using a Voltage-Gated Spin Hall-Effect Driven MTJ-based CrossbarChengmo Yang, Zeyu Chen. 195-200 [doi]
• Exploring Processing In-Memory for Different TechnologiesSaransh Gupta, Mohsen Imani, Tajana Rosing. 201-206 [doi]
• BLADE: A BitLine Accelerator for Devices on the EdgeWilliam Andrew Simon, Yasir Mahmood Qureshi, Alexandre Levisse, Marina Zapater, David Atienza. 207-212 [doi]
• Enhancing the Lifetime of Non-Volatile Caches by Exploiting Module-Wise Write RestrictionSukarn Agarwal, Hemangee K. Kapoor. 213-218 [doi]
• Mitigating the Performance and Quality of Parallelized Compressive Sensing Reconstruction Using Image StitchingMahmoud Namazi, Hosein Mohammadi Makrani, Zhi Tian, Setareh Rafatirad, Mohamad Hosein Akbari, Avesta Sasan, Houman Homayoun. 219-224 [doi]
• Towards Optimizing Refresh Energy in embedded-DRAM Caches using Private BlocksSheel Sindhu Manohar, Sukarn Agarwal, Hemangee K. Kapoor. 225-230 [doi]
• Extending Student Labs with SMT Circuit ImplementationErik Brunvand. 231-236 [doi]
• Teaching the Next Generation of Cryptographic Hardware Design to the Next Generation of EngineersAydin Aysu. 237-242 [doi]
• A Web-based Remote FPGA Laboratory for Computer Organization CourseHan Wan, Kangxu Liu, Jiazhen Lin, Xiaopeng Gao. 243-248 [doi]
• System-on-a-Chip Design as a Platform for Teaching Design and Design Flow IntegrationJacob Covey, Mark C. Johnson. 249-253 [doi]
• UPIM: Unipolar Switching Logic for High Density Processing-in-Memory ApplicationsJoonseop Sim, Saransh Gupta, Mohsen Imani, Yeseong Kim, Tajana Rosing. 255-258 [doi]
• Fence-Region-Aware Mixed-Height Standard Cell LegalizationSangGi Do, Mingyu Woo, Seokhyeong Kang. 259-262 [doi]
• A Case for Heterogeneous Network-on-Chip Based H.264 Video DecodersMilad Ghorbani Moghaddam, Cristinel Ababei. 263-266 [doi]
• A 16b Clockless Digital-to-Analog Converter with Ultra-Low-Cost Poly Resistors Supporting Wide-Temperature Range from -40°C to 85°CXuedi Wang, Xueqing Li, Longqiang Lai, Huazhong Yang. 267-270 [doi]
• A Skyrmion Racetrack Memory based Computing In-memory Architecture for Binary Neural Convolutional NetworkYu Pan, Peng Ouyang, Yinglin Zhao, Shouyi Yin, Youguang Zhang, Shaojun Wei, Weisheng Zhao. 271-274 [doi]
• TASecure: Temperature-Aware Secure Deletion Scheme for Solid State DrivesBingzhe Li, David H. C. Du. 275-278 [doi]
• An Asymmetric Dual Output On-Chip DC-DC Converter for Dynamic WorkloadsXingye Liu, Paul Ampadu. 279-282 [doi]
• CNNWire: Boosting Convolutional Neural Network with Winograd on ReRAM based AcceleratorsJilan Lin, Shuangchen Li, Xing Hu, Lei Deng, Yuan Xie. 283-286 [doi]
• Feed-Forward XOR PUFs: Reliability and Attack-Resistance AnalysisS. V. Sandeep Avvaru, Keshab K. Parhi. 287-290 [doi]
• Exploring Design Trade-offs in Fault-Tolerant Behavioral Hardware AcceleratorsZhiqi Zhu, Farah Naz Taher, Benjamin Carrión Schäfer. 291-294 [doi]
• Automatic Extraction of Requirements from State-based Hardware Designs for Runtime VerificationMinjun Seo, Roman Lysecky. 295-298 [doi]
• MirrorCache: An Energy-Efficient Relaxed Retention L1 STTRAM CacheKyle Kuan, Tosiron Adegbija. 299-302 [doi]
• Design and Evaluation of DNU-Tolerant Registers for Resilient Architectural State StorageFaris S. Alghareb, Ronald F. DeMara. 303-306 [doi]
• Automated Analysis of Virtual Prototypes at Electronic System LevelMehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler. 307-310 [doi]
• Dynamic Physically Unclonable FunctionsWenjie Xiong 0001, André Schaller, Stefan Katzenbeisser 0001, Jakub Szefer. 311-314 [doi]
• RDTA: An Efficient Routability-Driven Track Assignment AlgorithmGenggeng Liu, Zhen Zhuang, Wenzhong Guo, Ting-Chi Wang. 315-318 [doi]
• EraseMe: A Defense Mechanism against Information Leakage exploiting GPU MemoryHongyu Fang, Milos Doroslovacki, Guru Venkataramani. 319-322 [doi]
• A Statistical Current and Delay Model Based on Log-Skew-Normal Distribution for Low Voltage RegionPeng Cao 0002, Jiangping Wu, Zhiyuan Liu, Jingjing Guo, Jun Yang, Longxing Shi. 323-326 [doi]
• Enabling Approximate Storage through Lossy Media Data CompressionBrian Worek, Paul Ampadu. 327-330 [doi]
• Thermal Fingerprinting of FPGA Designs through High-Level SynthesisJianqi Chen, Benjamin Carrión Schäfer. 331-334 [doi]
• Deep RNN-Oriented Paradigm Shift through BOCANet: Broken Obfuscated Circuit AttackFatemeh Tehranipoor, Nima Karimian, Mehran Mozaffari Kermani, Hamid Mahmoodi. 335-338 [doi]
• STAT: Mean and Variance Characterization for Robust Inference of DNNs on Memristor-based PlatformsBaogang Zhang, Necati Uysal, Rickard Ewetz. 339-342 [doi]
• LSM: Novel Low-Complexity Unified Systolic Multiplier over Binary Extension FieldJiafeng Xie, Chiou-Yng Lee. 343-346 [doi]
• Binarized Depthwise Separable Neural Network for Object Tracking in FPGALi Yang, Zhezhi He, Deliang Fan. 347-350 [doi]
• An Analytical-based Hybrid Algorithm for FPGA PlacementChengyu Hu, Qinghua Duan, Liran Hu, Peng Lu, Zhengjie Li, Meng Yang, Jian Wang, Jinmei Lai. 351-354 [doi]
• Approximate Memory with Approximate DCTShenghou Ma, Paul Ampadu. 355-358 [doi]
• AQuRate: MRAM-based Stochastic Oscillator for Adaptive Quantization Rate Sampling of Sparse SignalsSoheil Salehi, Ramtin Zand, Alireza Zaeemzadeh, Nazanin Rahnavard, Ronald F. DeMara. 359-362 [doi]
• Clockless Spin-based Look-Up Tables with Wide Read MarginSoheil Salehi, Ramtin Zand, Ronald F. DeMara. 363-366 [doi]
• A Hybrid Framework for Functional Verification using Reinforcement Learning and Deep LearningKarunveer Singh, Rishabh Gupta, Vikram Gupta, Arash Fayyazi, Massoud Pedram, Shahin Nazarian. 367-370 [doi]
• Digital and Analog-Mixed-Signal In-Memory Processing in CMOS SRAMAkhilesh Jaiswal, Amogh Agrawal, Indranil Chakraborty, Mustafa Fayez Ali, Kaushik Roy 0001. 371 [doi]
• Ferroelectric FET Based In-Memory Computing for Few-Shot LearningAnn Franchesca Laguna, Xunzhao Yin, Dayane Reis, Michael T. Niemier, Xiaobo Sharon Hu. 373-378 [doi]
• True In-memory Computing with the CRAM: From Technology to ApplicationsMasoud Zabihi, Zhengyang Zhao, Zamshed I. Chowdhury, Salonik Resch, Mahendra DC, Thomas Peterson, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar. 379 [doi]
• An Overview of In-memory Processing with Emerging Non-volatile Memory for Data-intensive ApplicationsBing Li, Bonan Yan, Hai Li. 381-386 [doi]
• Security Threats in Approximate Computing SystemsPruthvy Yellu, Novak Boskov, Michel A. Kinsy, Qiaoyan Yu. 387-392 [doi]
• Characterizing Approximate Adders and Multipliers Optimized under Different Design ConstraintsHonglan Jiang, Francisco J. H. Santiago, Mohammad Saeed Ansari, Leibo Liu, Bruce F. Cockburn, Fabrizio Lombardi, Jie Han 0001. 393-398 [doi]
• Approximate Communication Strategies for Energy-Efficient and High Performance NoC: Opportunities and ChallengesMd Farhadur Reza, Paul Ampadu. 399-404 [doi]
• Information Hiding behind Approximate ComputationYe Wang, Qian Xu, Gang Qu, Jian Dong. 405-410 [doi]
• MLPrivacyGuard: Defeating Confidence Information based Model Inversion Attacks on Machine Learning SystemsTiago A. O. Alves, Felipe M. G. França, Sandip Kundu. 411-415 [doi]
• XNOR-SRAM: In-Bitcell Computing SRAM Macro based on Resistive Computing MechanismZhewei Jiang, Shihui Yin, Jae-sun Seo, Mingoo Seok. 417-422 [doi]
• Efficient Process-in-Memory Architecture Design for Unsupervised GAN-based Deep Learning using ReRAMFan Chen, Linghao Song, Hai (Helen) Li. 423-428 [doi]
• DigitalPIM: Digital-based Processing In-Memory for Big Data AccelerationMohsen Imani, Saransh Gupta, Yeseong Kim, Minxuan Zhou, Tajana Rosing. 429-434 [doi]
• In-memory Processing based on Time-domain CircuitYuyao Kong, Jun Yang. 435-438 [doi]
• An Overview of Thermal Challenges and Opportunities for Monolithic 3D ICsPrachi Shukla, Ayse Kivilcim Coskun, Vasilis F. Pavlidis, Emre Salman. 439-444 [doi]
• Logic Monolithic 3D ICs: PPA Benefits and EDA Tools NecessarySai Surya Kiran Pentapati, Da Eun Shim, Sung Kyu Lim. 445-450 [doi]
• Investigation and Trade-offs in 3DIC Partitioning Methodologies: N/ANikolaos Sketopoulos, Christos P. Sotiriou, Vasileios Samaras. 451-455 [doi]
• Test and Design-for-Testability Solutions for Monolithic 3D Integrated CircuitsAbhishek Koneru, Krishnendu Chakrabarty. 457-462 [doi]
• N3XT Monolithic 3D Energy-Efficient Computing SystemsMohamed M. Sabry Aly. 463 [doi]
• How to Generate Robust Keys from Noisy DRAMs?Nima Karimian, Fatemeh Tehranipoor. 465-469 [doi]
• Threats on Logic Locking: A Decade LaterKimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan. 471-476 [doi]
• On Custom LUT-based ObfuscationGaurav Kolhe, Sai Manoj P. D., Setareh Rafatirad, Hamid Mahmoodi, Avesta Sasan, Houman Homayoun. 477-482 [doi]
• Securing Analog Mixed-Signal Integrated Circuits Through Shared DependenciesKyle Juretus, Vaibhav Venugopal Rao, Ioannis Savidis. 483-488 [doi]
• Design Methodology for Embedded Approximate Artificial Neural NetworksAdarsha Balaji, Salim Ullah, Anup Das 0001, Akash Kumar 0001. 489-494 [doi]
• Exploration of Segmented Bus As Scalable Global Interconnect for Neuromorphic ComputingAdarsha Balaji, Yuefeng Wu, Anup Das 0001, Francky Catthoor, Siebren Schaafsma. 495-499 [doi]
• ADMM-based Weight Pruning for Real-Time Deep Learning Acceleration on Mobile DevicesHongjia Li, Ning Liu, Xiaolong Ma, Sheng Lin, Shaokai Ye, Tianyun Zhang, Xue Lin, Wenyao Xu, Yanzhi Wang. 501-506 [doi]
• On the use of Deep Autoencoders for Efficient Embedded Reinforcement LearningBharat Prakash, Mark Horton, Nicholas R. Waytowich, William David Hairston, Tim Oates, Tinoosh Mohsenin. 507-512 [doi]
• Tuning Track-based NVM Caches for Low-Power IoT DevicesHoda Aghaei Khouzani, Chengmo Yang. 513-518 [doi]
• Dynamic Computation Migration at the Edge: Is There an Optimal Choice?Sina Shahhosseini, Iman Azimi, Arman Anzanpour, Axel Jantsch, Pasi Liljeberg, Nikil D. Dutt, Amir M. Rahmani. 519-524 [doi]
• Solving Energy and Cybersecurity Constraints in IoT Devices Using Energy Recovery ComputingHimanshu Thapliyal, Zachary Kahleifeh. 525-530 [doi]
• Right-Provisioned IoT Edge Computing: An OverviewTosiron Adegbija, Roman Lysecky, Vinu Vijay Kumar. 531-536 [doi]
• Secure Computing Systems Design Through Formal Micro-ContractsMichel A. Kinsy, Novak Boskov. 537-542 [doi]