Abstract is missing.
- RISC assessment: A high-level language experimentDavid A. Patterson, Richard S. Piepho. 3-8 [doi]
- Measurement and analysis of instruction use in the VAX-11/780Douglas W. Clark, Henry M. Levy. 9-17 [doi]
- HLL architectures: Pitfalls and predilectionsKrishna M. Kavi, Boumediene Belkhouche, Evelyn Bullard, Lois M. L. Delcambre, Stephen M. Nemecek. 18-23 [doi]
- The NYU Ultracomputer-designing a MIMD, shared-memory parallel machine (Extended Abstract)Allan Gottlieb, Ralph Grishman, Clyde P. Kruskal, Kevin P. McAuliffe, Larry Rudolph, Marc Snir. 27-42 [doi]
- VLSI architectures for high speed recognition of context-free languages and finite-state languagesKing-Hang Chu, King-sun Fu. 43-49 [doi]
- Asynchronous and clocked control structures for VLSI based interconnection networksMark A. Franklin, Donald F. Wann. 50-59 [doi]
- Performance and fault tolerance improvements in the Inverse Augmented Data Manipulator networkRobert J. McMillen, Howard Jay Siegel. 63-72 [doi]
- The Gamma network: A multiprocessor interconnection network with redundant pathsD. S. Parker, C. S. Raghavendra. 73-80 [doi]
- A control processor for a reconfigurable array computerRoy M. Jenevein, James C. Browne. 81-89 [doi]
- A general class of processor interconnection strategiesLaxmi N. Bhuyan, Dharma P. Agrawal. 90-98 [doi]
- Instruction set design issues relating to a static dataflow computerForbes J. Burkowski. 101-111 [doi]
- Decoupled access/execute computer architecturesJames E. Smith. 112-119 [doi]
- A data flow architecture with a paged memory systemL. J. Caluwaerts, J. Debacker, J. A. Peperstraete. 120-127 [doi]
- Efficient code generation for horizontal architectures: Compiler techniques and architectural supportB. Ramakrishna Rau, Christopher D. Glaeser, Raymond L. Picard. 131-139 [doi]
- Sentry: A novel hardware implementation of classic operating system mechanismsGene C. Barton. 140-147 [doi]
- A logic simulation machineMiron Abramovici, Ytzhak H. Levendel, Premachandran R. Menon. 148-157 [doi]
- Towards a family of languages for the design and implementation of machine architecturesSubrata Dasgupta, Marius Olafsson. 158-167 [doi]
- Design of a 2 × 2 fault-tolerant switching elementWoei Lin, Chuan-lin Wu. 181-189 [doi]
- Fault-tolerant wafer-scale architectures for VLSIDonald S. Fussell, Peter J. Varman. 190-198 [doi]
- Database filtersSakti Pramanik. 201-210 [doi]
- On the semantic structure of information - A proposal of the abstract storage architectureMario Tokoro, Takashi Takizuka. 211-217 [doi]
- Hardware sorter and its application to data base machineYasunori Dohi, Akira Suzuki, Noriyuki Matsui. 218-225 [doi]
- A recursive computer architecture for VLSIPhilip C. Treleaven, Richard P. Hopkins. 229-238 [doi]
- µ3L: An HLL-RISC processor for parallel execution of FP-language programsM. Castan, Elliott I. Organick. 239-247 [doi]
- The heap/substitution concept - an implementation of functional operations on data structures for a reduction machineFerdinand Hommes. 248-256 [doi]
- A shared resource algorithm for distributed simulationPaul F. Reynolds Jr.. 259-266 [doi]
- Duplication of packets and their detection in X.25 communication protocolsBijendra N. Jain. 267-273 [doi]
- A multiple processor system for real time control tasksPauline Markenscoff. 274-280 [doi]
- A heterogeneous multiprocessor design and the distributed scheduling of its task group workloadLeslie Jill Miller. 283-290 [doi]
- A dual processor VAX 11/780George H. Goble, Michael H. Marsh. 291-298 [doi]
- Effects of cache coherency in multiprocessorsMichel Dubois, Faye A. Briggs. 299-308 [doi]
- Probabilistic analysis of a crossbar switchTrevor N. Mudge, B. A. Makrucki. 311-320 [doi]
- Finding an extremum in a networkSteven P. Levitan, Caxton C. Foster. 321-325 [doi]
- Resource allocation in rectangular SW banyansU. V. Premkumar, James C. Browne. 326-333 [doi]