Table of Contents

• Moving the needle, computer architecture research in academe and industryWilliam J. Dally. 1 [doi]
• WiDGET: Wisconsin decoupled grid execution tilesYasuko Watanabe, John D. Davis, David A. Wood. 2-13 [doi]
• Forwardflow: a scalable core for power-constrained CMPsDan Gibson, David A. Wood. 14-25 [doi]
• Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysisOmid Azizi, Aqeel Mahesri, Benjamin C. Lee, Sanjay J. Patel, Mark Horowitz. 26-36 [doi]
• Understanding sources of inefficiency in general-purpose chipsRehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz. 37-47 [doi]
• Translation caching: skip, don t walk (the page table)Thomas W. Barr, Alan L. Cox, Scott Rixner. 48-59 [doi]
• High performance cache replacement using re-reference interval prediction (RRIP)Aamer Jaleel, Kevin B. Theobald, Simon C. Steely Jr., Joel S. Emer. 60-71 [doi]
• The virtual write queue: coordinating DRAM and last-level cache policiesJeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John. 72-82 [doi]
• Reducing cache power with low-cost, multi-bit error-correcting codesChris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, Shih-Lien Lu. 83-93 [doi]
• An intra-chip free-space optical interconnectJing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang, Ioannis Savidis, Manish Jain, Rebecca Berman, Peng Liu, Michael C. Huang, Hui Wu, Eby G. Friedman, Gary Wicks, Duncan Moore. 94-105 [doi]
• Aérgia: exploiting packet latency slack in on-chip networksReetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das. 106-116 [doi]
• Silicon-photonic network architectures for scalable, power-efficient multi-chip systemsPranay Koka, Michael O. McCracken, Herb Schwetman, Xuezhe Zheng, Ron Ho, Ashok V. Krishnamoorthy. 117-128 [doi]
• Re-architecting DRAM memory systems with monolithically integrated silicon photonicsScott Beamer, Chen Sun, Yong Jin Kwon, Ajay Joshi, Christopher Batten, Vladimir Stojanovic, Krste Asanovic. 129-140 [doi]
• Use ECP, not ECC, for hard failures in resistive memoriesStuart E. Schechter, Gabriel H. Loh, Karin Straus, Doug Burger. 141-152 [doi]
• Morphable memory system: a robust architecture for exploiting multi-level phase change memoriesMoinuddin K. Qureshi, Michele Franceschini, Luis Alfonso Lastras-Montaño, John P. Karidis. 153-162 [doi]
• SieveStore: a highly-selective, ensemble-level disk cache for cost-performanceTimothy Pritchett, Mithuna Thottethodi. 163-174 [doi]
• Rethinking DRAM design and organization for energy-constrained multi-coresAniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi. 175-186 [doi]
• LReplay: a pending period based deterministic replay schemeYunji Chen, Weiwu Hu, Tianshi Chen, Ruiyang Wu. 187-197 [doi]
• Timetraveler: exploiting acyclic races for optimizing memory race recordingGwendolyn Voskuilen, Faraz Ahmad, T. N. Vijaykumar. 198-209 [doi]
• Conflict exceptions: simplifying concurrent language semantics with precise hardware exceptions for data-racesBrandon Lucia, Luis Ceze, Karin Strauss, Shaz Qadeer, Hans-Juergen Boehm. 210-221 [doi]
• ColorSafe: architectural support for debugging and dynamically avoiding multi-variable atomicity violationsBrandon Lucia, Luis Ceze, Karin Strauss. 222-233 [doi]
• Shared caches in multicores: the good, the bad, and the uglyMary Jane Irwin. 234 [doi]
• Dynamic warp subdivision for integrated branch and memory divergence toleranceJiayuan Meng, David Tarjan, Kevin Skadron. 235-246 [doi]
• A dynamically configurable coprocessor for convolutional neural networksSrimat T. Chakradhar, Murugan Sankaradass, Venkata Jakkula, Srihari Cadambi. 247-257 [doi]
• RETCON: transactional repair without replayColin Blundell, Arun Raghavan, Milo M. K. Martin. 258-269 [doi]
• Thread tailor: dynamically weaving threads together for efficient, adaptive parallel applicationsJanghaeng Lee, Haicheng Wu, Madhumitha Ravichandran, Nathan Clark. 270-279 [doi]
• An integrated GPU power and performance modelSunpyo Hong, Hyesoon Kim. 280-289 [doi]
• A case for FAME: FPGA architecture model executionZhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bird, Krste Asanovic, David A. Patterson. 290-301 [doi]
• Evolution of thread-level parallelism in desktop applicationsGeoffrey Blake, Ronald G. Dreslinski, Trevor N. Mudge, Krisztián Flautner. 302-313 [doi]
• Web search using mobile cores: quantifying and mitigating the price of efficiencyVijay Janapa Reddi, Benjamin C. Lee, Trishul M. Chilimbi, Kushagra Vaid. 314-325 [doi]
• The impact of management operations on the virtualized datacenterVijayaraghavan Soundararajan, Jennifer M. Anderson. 326-337 [doi]
• Energy proportional datacenter networksDennis Abts, Michael R. Marty, Philip M. Wells, Peter Klausler, Hong Liu. 338-347 [doi]
• Improving the future by examining the pastCharles P. Thacker. 348 [doi]
• The rebirth of neural networksOlivier Temam. 349 [doi]
• NoHype: virtualized cloud infrastructure without the virtualizationEric Keller, Jakub Szefer, Jennifer Rexford, Ruby B. Lee. 350-361 [doi]
• Modeling critical sections in Amdahl s law and its implications for multicore designStijn Eyerman, Lieven Eeckhout. 362-370 [doi]
• Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computingXiaochen Guo, Engin Ipek, Tolga Soyata. 371-382 [doi]
• Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mappingNak Hee Seong, Dong Hyuk Woo, Hsien-Hsin S. Lee. 383-394 [doi]
• IVEC: off-chip memory integrity protection for both security and reliabilityRuirui Huang, G. Edward Suh. 395-406 [doi]
• Sentry: light-weight auxiliary memory access controlArrvindh Shriraman, Sandhya Dwarkadas. 407-418 [doi]
• Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessorsEnric Herrero, José González, Ramon Canal. 419-428 [doi]
• Cohesion: a hybrid memory model for acceleratorsJohn H. Kelm, Daniel R. Johnson, William Tuohy, Steven S. Lumetta, Sanjay J. Patel. 429-440 [doi]
• Data marshaling for multi-core architecturesM. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt. 441-450 [doi]
• Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPUVictor W. Lee, Changkyu Kim, Jatin Chhugani, Michael Deisher, Daehyun Kim, Anthony D. Nguyen, Nadathur Satish, Mikhail Smelyanskiy, Srinivas Chennupaty, Per Hammarlund, Ronak Singhal, Pradeep Dubey. 451-460 [doi]
• Using hardware vulnerability factors to enhance AVF analysisVilas Sridharan, David R. Kaeli. 461-472 [doi]
• Necromancer: enhancing system throughput by animating dead coresAmin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke. 473-484 [doi]
• Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processorsGuihai Yan, Xiaoyao Liang, Yinhe Han, Xiaowei Li. 485-496 [doi]
• Relax: an architectural framework for software recovery of hardware faultsMarc de Kruijf, Shuou Nomura, Karthikeyan Sankaralingam. 497-508 [doi]