Table of Contents

• Nanotechnology for low-power and high-speed nanoelectronics applicationsRobert Chau. 1 [doi]
• Compact modeling of carbon nanotube transistor for early stage process-design explorationAsha Balijepalli, Saurabh Sinha, Yu Cao. 2-7 [doi]
• A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologiesRajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang. 8-13 [doi]
• Low power FPGA design using hybrid CMOS-NEMS approachYu Zhou, Shijo Thekkel, Swarup Bhunia. 14-19 [doi]
• Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologiesSaibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang. 20-25 [doi]
• Clocking structures and power analysis for nanomagnet-based logic devicesMichael T. Niemier, M. Alam, Xiaobo Sharon Hu, Gary H. Bernstein, Wolfgang Porod, M. Putney, J. DeAngelis. 26-31 [doi]
• Energy efficient near-threshold chip multi-processingBo Zhai, Ronald G. Dreslinski, David Blaauw, Trevor N. Mudge, Dennis Sylvester. 32-37 [doi]
• Analysis of dynamic voltage/frequency scaling in chip-multiprocessorsSebastian Herbert, Diana Marculescu. 38-43 [doi]
• Evaluating design tradeoffs in on-chip power management for CMPsJoseph J. Sharkey, Alper Buyuktosunoglu, Pradip Bose. 44-49 [doi]
• Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processorsKeith A. Bowman, Alaa R. Alameldeen, Srikanth T. Srinivasan, Chris Wilkerson. 50-55 [doi]
• A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 cachesSungjune Youn, Hyunhee Kim, Jihong Kim. 56-61 [doi]
• Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distributionSherif A. Tawfik, Volkan Kursun. 62-67 [doi]
• A robust edge encoding technique for energy-efficient multi-cycle interconnectJae-sun Seo, Dennis Sylvester, David Blaauw, Himanshu Kaul, Ram Krishnamurthy. 68-73 [doi]
• Low-power process-variation tolerant arithmetic units using input-based elastic clockingDebabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy. 74-79 [doi]
• Sleep transistor sizing and control for resonant supply noise dampingJie Gu, Hanyong Eom, Chris H. Kim. 80-85 [doi]
• Thermal-aware methodology for repeater insertion in low-power VLSI circuitsJa Chun Ku, Yehea I. Ismail. 86-91 [doi]
• Post-placement leakage optimization for partially dynamically reconfigurable FPGAsChi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang. 92-97 [doi]
• Power optimal MTCMOS repeater insertion for global busesHanif Fatemi, Behnam Amelifard, Massoud Pedram. 98-103 [doi]
• Timing-driven row-based power gatingAshoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino. 104-109 [doi]
• Detailed placement for leakage reduction using systematic through-pitch variationAndrew B. Kahng, Swamy Muddu, Puneet Sharma. 110-115 [doi]
• Early power grid verification under circuit current uncertaintiesImad A. Ferzli, Farid N. Najm, Lars Kruse. 116-121 [doi]
• Future of on-chip interconnection architecturesShekhar Borkar, William J. Dally. 122 [doi]
• Towards a software approach to mitigate voltage emergenciesMeeta Sharma Gupta, Krishna K. Rangan, Michael D. Smith, Gu-Yeon Wei, David Brooks. 123-128 [doi]
• Improving disk reuse for reducing power consumptionMahmut T. Kandemir, Seung Woo Son, Mustafa Karaköy. 129-134 [doi]
• PVS: passive voltage scaling for wireless sensor networksYoungjin Cho, Younghyun Kim, Naehyuck Chang. 135-140 [doi]
• A programming environment with runtime energy characterization for energy-aware applicationsChangjiu Xian, Yung-Hsiang Lu, Zhiyuan Li. 141-146 [doi]
• A process variation aware low power synthesis methodology for fixed-point FIR filtersNilanjan Banerjee, Jung Hwan Choi, Kaushik Roy. 147-152 [doi]
• Voltage- and ABB-island optimization in high level synthesisDomenik Helms, Olaf Meyer, Marko Hoyer, Wolfgang Nebel. 153-158 [doi]
• Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologiesSimone Medardoni, Davide Bertozzi, Enrico Macii. 159-164 [doi]
• Power signal processing: a new perspective for power analysis and optimizationQuming Zhou, Lin Zhong, Kartik Mohanram. 165-170 [doi]
• A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAMJaydeep P. Kulkarni, Keejong Kim, Kaushik Roy. 171-176 [doi]
• A low-power SRAM using bit-line charge-recycling techniqueKeejong Kim, Hamid Mahmoodi, Kaushik Roy. 177-182 [doi]
• Minimizing power dissipation during write operation to register filesKimish Patel, Wonbok Lee, Massoud Pedram. 183-188 [doi]
• An on-chip NBTI sensor for measuring PMOS threshold voltage degradationJohn Keane, Tae-Hyoung Kim, Chris H. Kim. 189-194 [doi]
• Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTIYiran Chen, Hai Li, Jing Li, Cheng-Kok Koh. 195-200 [doi]
• Throughput of multi-core processors under thermal constraintsRavishankar Rao, Sarma B. K. Vrudhula, Chaitali Chakrabarti. 201-206 [doi]
• Dynamic voltage frequency scaling for multi-tasking systems using online learningGaurav Dhiman, Tajana Simunic Rosing. 207-212 [doi]
• Thermal-aware task scheduling at the system software levelJeonghwan Choi, Chen-Yong Cher, Hubertus Franke, Henrdrik Hamann, Alan J. Weger, Pradip Bose. 213-218 [doi]
• Thermal response to DVFS: analysis with an Intel Pentium MHeather Hanson, Stephen W. Keckler, Soraya Ghiasi, Karthick Rajamani, Freeman L. Rawson III, Juan Rubio. 219-224 [doi]
• Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedulesSushu Zhang, Karam S. Chatha, Goran Konjevod. 225-230 [doi]
• The parallel computing landscape: a Berkeley viewDavid A. Patterson. 231 [doi]
• Low power soft-output signal detector design for wireless MIMO communication systemsSizhong Chen, Tong Zhang. 232-237 [doi]
• A low power multimedia SoC with fully programmable 3D graphics and MPEG4/H.264/JPEG for mobile devicesJeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, Jongcheol Jeong, Euljoo Jeong, Suk Joong Lee, Hoi-Jun Yoo. 238-243 [doi]
• An architecture for energy efficient sphere decodingRavi Jenkal, W. Rhett Davis. 244-249 [doi]
• On the selection of arithmetic unit structure in voltage overscaled soft digital signal processingYang Liu, Tong Zhang. 250-255 [doi]
• Low-power H.264/AVC baseline decoder for portable applicationsKe Xu, Chiu-sing Choy. 256-261 [doi]
• A 0.4-V UWB baseband processorVivienne Sze, Anantha P. Chandrakasan. 262-267 [doi]
• Resource area dilation to reduce power density in throughput serversMichael D. Powell, T. N. Vijaykumar. 268-273 [doi]
• Locality-driven architectural cache sub-banking for leakage energy reductionOlga Golubeva, Mirko Loghi, Enrico Macii, Massimo Poncino. 274-279 [doi]
• A multi-model power estimation engine for accuracy optimizationFelipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. dos Santos. 280-285 [doi]
• A fast-transient over-sampled delta-sigma adaptive DC-DC converter for power-efficient noise-sensitive devicesMinkyu Song, Dongsheng Ma. 286-291 [doi]
• High-efficiency synchronous dual-output switched-capacitor dc-dc converter with digital state machine controlHan Shiming, Wu Xiaobo, Liu Yang. 292-297 [doi]
• A micro power management system and maximum output power control for solar energy harvesting applicationsHui Shao, Chi-Ying Tsui, Wing-Hung Ki. 298-303 [doi]
• Advanced thermal sensing circuit and test techniques used in a high performance 65nm processorDavid E. Duarte, Greg Taylor, Keng L. Wong, Usman Mughal, George Geannopoulos. 304-309 [doi]
• Single inductor, multiple input, multiple output (SIMIMO) power mixer-charger-supply systemMin Chen, Gabriel A. Rincón-Mora. 310-315 [doi]
• Vibration energy scavenging and management for ultra low power applicationsLu Chao, Chi-Ying Tsui, Wing-Hung Ki. 316-321 [doi]
• Energy management of DVS-DPM enabled embedded systems powered by fuel cell-battery hybrid sourceJianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang. 322-327 [doi]
• Design of an efficient power delivery network in an soc to enable dynamic power managementBehnam Amelifard, Massoud Pedram. 328-333 [doi]
• Energy-efficient and performance-enhanced disks using flash-memory cacheJen-Wei Hsieh, Tei-Wei Kuo, Po-Liang Wu, Yu-Chung Huang. 334-339 [doi]
• SAPP: scalable and adaptable peak power management in nocsPraveen Bhojwani, Jason D. Lee, Rabi N. Mahapatra. 340-345 [doi]
• All watts consideredLuiz André Barroso. 346 [doi]
• A 65-nm pulsed latch with a single clocked transistorMartin Saint-Laurent, Baker Mohammad, Paul Bassett. 347-350 [doi]
• A methodology for analysis and verification of power gated circuits with correlated resultsAveek Sarkar, Shen Lin, Kai Wang. 351-354 [doi]
• V::t:: balancing and device sizing towards high yield of sub-threshold static logic gatesYu Pu, Jose de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha. 355-358 [doi]
• Power-efficient LDPC code decoder architectureKazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto. 359-362 [doi]
• A low-power CSCD asynchronous viterbi decoder for wireless applicationsMohamed Kawokgy, C. Andre T. Salama. 363-366 [doi]
• Reducing cache energy consumption by tag encoding in embedded processorsMingming Zhang, Xiaotao Chang, Ge Zhang. 367-370 [doi]
• On reducing energy-consumption by late-inserting instructions into the issue queueEnric Morancho, José María Llabería, Àngel Olivé. 371-374 [doi]
• Power-aware operand deliveryErika Gunadi, Mikko H. Lipasti. 375-378 [doi]
• On the latency, energy and area of checkpointed, superscalar register alias tablesElham Safi, Patrick Akl, Andreas Moshovos, Andreas G. Veneris, Aggeliki Arapoyanni. 379-382 [doi]
• Adaptive analog biasing: a robustness-enhanced low-power technique for analog baseband designZhenhua Wang. 383-386 [doi]
• Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gatesMyeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy. 387-390 [doi]
• Electromigration and voltage drop aware power grid optimization for power gated ICsAida Todri, Shih-Chieh Chang, Malgorzata Marek-Sadowska. 391-394 [doi]
• Reducing display power in DVS-enabled handheld systemsJung-Hi Min, Hojung Cha. 395-398 [doi]
• Multicasting based topology generation and core mapping for a power efficient networks-on-chipBalasubramanian Sethuraman, Ranga Vemuri. 399-402 [doi]
• Phase-aware adaptive hardware selection for power-efficient scientific computationsKonrad Malkowski, Padma Raghavan, Mahmut T. Kandemir, Mary Jane Irwin. 403-406 [doi]
• Signoff power methodology for contactless smartcardsJulien Mercier, Christian Dufaza, Mathieu Lisart. 407-410 [doi]
• An ilp based approach to reducing energy consumption in nocbased CMPSOzcan Ozturk, Mahmut T. Kandemir, Seung Woo Son. 411-414 [doi]