Table of Contents

• The 4-Diamond Circuit - A Minimally Complex Nano-Scale Computational Building Block in QCAMichael T. Niemier, Peter M. Kogge. 3-10 [doi]
• Decoding of Stochastically Assembled NanoarraysBenjamin Gojman, Eric Rachlin, John E. Savage. 11-18 [doi]
• The NanoBox Project: Exploring Fabrics of Self-Correcting Logic Blocks for High Defect Rate Molecular Device TechnologiesA. J. KleinOsowski, David J. Lilja. 19-24 [doi]
• NANOLAB: A Tool for Evaluating Reliability of Defect-Tolerant Nano ArchitecturesDebayan Bhaduri, Sandeep K. Shukla. 25-31 [doi]
• A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence CheckingLun Li, Mitchell A. Thornton, Stephen A. Szygenda. 32-38 [doi]
• System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC ArchitecturesKrishnan Srinivasan, Nagender Telkar, Vijay Ramamurthi, Karam S. Chatha. 39-45 [doi]
• Fault Tolerant Algorithms for Network-On-Chip InterconnectMatthew Pirretti, Greg M. Link, Richard R. Brooks, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. 46-51 [doi]
• A Comparative Study of Modeling at Different Levels of Abstraction in System on Chip Designs: A Case StudySuryaprasad Jayadevappa, Ravi Shankar, Imad Mahgoub. 52-60 [doi]
• Energy Evaluation Methodology for Platform Based System-on-Chip DesignKristian Hildingsson, Tughrul Arslan, Ahmet T. Erdogan. 61-68 [doi]
• Comparison between Different Data Buses ConfigurationsAlain Lopez, Denis Deschacht. 69-76 [doi]
• Evaluating Alternative Implementations for LDPC Decoder Check Node FunctionTheo Theocharides, Greg M. Link, Eric J. Swankoski, Narayanan Vijaykrishnan, Mary Jane Irwin, Herman Schmit. 77-82 [doi]
• Minimum Area Cost for a 30 to 70 Gbits/s AES ProcessorAlireza Hodjat, Ingrid Verbauwhede. 83-88 [doi]
• A Review of Large Parallel Counter DesignsEarl E. Swartzlander Jr.. 89-98 [doi]
• Behavioural Scheduling to Balance the Bit-Level Computational EffortMaría C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida. 99-104 [doi]
• WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM ArraysMahadevan Gomathisankaran, Akhilesh Tyagi. 105-114 [doi]
• New Bulk Dynamic Threshold NMOS Schemes for Low-Energy Subthreshold Domino-Like CircuiWalid Elgharbawy, Magdy A. Bayoumi. 115-120 [doi]
• Suppression of Jitter Effects in A/D Converters through Sigma-Delta SamplingAdam Strak, Hannu Tenhunen. 121-126 [doi]
• Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic ApproachPeter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis. 127-134 [doi]
• Experimental Evaluation of Resonant Clock DistributionJuang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou. 135-140 [doi]
• A Double-Edge Implicit-Pulsed Level Convert Flip-FlopPeiyi Zhao, Golconda Pradeep Kumar, C. Archana, Magdy A. Bayoumi. 141-144 [doi]
• Fixed-Load Energy Recovery Memory for Low PowerJoohee Kim, Conrad H. Ziesler. 145-150 [doi]
• Multi-Parameter Power Minimization of Synthesized DatapathsW. Rhett Davis, Ambarish M. Sule, Hao Hua. 151-157 [doi]
• Usage of Application-Specific Switching Activity for Energy Minimization of Arithmetic UnitsShu-Shin Chin, Sangjin Hong, Suhwan Kim. 158-166 [doi]
• Enhancement of the Illinois Scan Architecture for Use with Multiple Scan InputsMihir A. Shah, Janak H. Patel. 167-172 [doi]
• Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BISTChunsheng Liu, Kumar N. Dwarakanath, Krishnendu Chakrabarty, Ronald D. Blanton. 173-178 [doi]
• Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning ConstraintsMakoto Sugihara, Kazuaki Murakami, Yusuke Matsunaga. 179-186 [doi]
• Control and Data Flow Graph Extraction for High-Level SynthesisRavi Namballa, Nagarajan Ranganathan, Abdel Ejnioui. 192 [doi]
• Force-Directed Performance-Driven Placement Algorithm for FPGAsHao Li, Wai-Kei Mak, Srinivas Katkoori. 193-198 [doi]
• Stochastic Modeling Based Environment for Synthesis and Comparison of Bus Arbitration PoliciesSankalp Kallakuri, Alex Doboli, Simona Doboli. 199-206 [doi]
• DREAM: A Chip-Package Co-Design Tool for RF-Mixed Signal SystemsGhanshyam Nayak, Tejasvi Das, T. M. Rao, P. R. Mukund. 207-210 [doi]
• Low Power 2.5 Gb/s Serializer for SOC ApplicationsKrzysztof Iniewski, Marek Syrzycki. 211-212 [doi]
• A 2.4 GHz Low-Power Low-Phase-Noise CMOS LC VCOJie Long, Jo Yi Foo, Robert J. Weber. 213-214 [doi]
• Reconfigurability-Power Trade-Offs in Turbo Decoder Design and ImplementationIndrajit Atluri, Tughrul Arslan. 215-217 [doi]
• A Low Voltage to High Voltage Level Shifter in a Low Voltage, 0.25 µm, PD SOI ProcessErik J. Mentze, Kevin M. Buck, Herbert L. Hess, David F. Cox, Mohammad M. Mojarradi. 218-221 [doi]
• Design and Implementation of Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAsAbdsamad Benkrid, Khaled Benkrid, Danny Crookes. 222-225 [doi]
• Low Power FIR Filter Implementations Based on Coefficient Ordering AlgorithmAhmet T. Erdogan, Tughrul Arslan. 226-228 [doi]
• A High-Level Implementation of a High Performance Pipeline FFT on Virtex-E FPGAsS. Sukhsawas, Khaled Benkrid. 229-232 [doi]
• 64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor LogiKuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao. 233-236 [doi]
• Implementation of JPEG2000 Arithmetic Decoder on a Dynamically Reconfigurable ATMEL FPGASophie Bouchoux, El-Bay Bourennane, Johel Mitéran, Michel Paindavoine. 237-238 [doi]
• Congestion Estimation for 3D RoutingLerong Cheng, William N. N. Hung, Guowu Yang, Xiaoyu Song. 239-240 [doi]
• Towards a Heterogeneous Simulation Kernel for System Level Models: A SystemC Kernel for Synchronous Data Flow ModelsHiren D. Patel, Sandeep K. Shukla. 241-242 [doi]
• Low-Power Field-Programmable VLSI Processor Using Dynamic CircuitsWeisheng Chong, Masanori Hariyama, Michitaka Kameyama. 243-248 [doi]
• Incorporating Power Reduction Mechanism in Arithmetic Core DesignSangjin Hong, Shu-Shin Chin. 249-250 [doi]
• Multioperand Decimal AdditionRobert D. Kenney, Michael J. Schulte. 251-253 [doi]
• Pipeline Design Based on Self-Resetting Stage LogicAbdel Ejnioui, Abdelhalim Alsharqawi. 254-257 [doi]
• Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array StructureNaotaka Ohsawa, Osamu Sakamoto, Masanori Hariyama, Michitaka Kameyama. 258-259 [doi]
• Tabu Search Based Behavioral Synthesis of Low Leakage DatapathsChandramouli Gopalakrishnan, Srinivas Katkoori. 260-261 [doi]
• On the Reduction of Simultaneous Switching in SoCsArindam Mukherjee. 262-263 [doi]
• OSIRIS: Automated Synthesis of Flat and Hierarchical Bus Architectures for Deep Submicron Systems on ChipNattawut Thepayasuwan, Alex Doboli. 264-265 [doi]
• A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable ArchitecturePeter Zipf, Claude Stötzler, Manfred Glesner. 266-267 [doi]
• Integrated VLSI Potentiostat for Cyclic Voltammetry in Electrolytic ReactionsHarpreet S. Narula, John G. Harris. 268-270 [doi]
• Handling Data Streams while Compiling C Programs onto HardwareRajarshi Mukherjee, Alex K. Jones, Prithviraj Banerjee. 271-272 [doi]
• A Subword-Parallel Multiplication and Sum-of-Squares UnitShankar Krithivasan, Michael J. Schulte, John Glossner. 273-274 [doi]
• Hybrid Parallel Counters - Domino and Threshold LogicTroy D. Townsend, Peter Celinski, Said F. Al-Sarawi, Michael J. Liebelt. 275-276 [doi]
• Two-Dimensional Folding Strategies for Improved Layouts of Cyclic ShiftersPeter-Michael Seidel, Kenneth Fazel. 277-278 [doi]
• A Memory Aware High Level Synthesis Tool Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin. 279-280 [doi]
• Scan Cell Ordering for Low Power BISTMaciej Bellos, Dimitris Bakalis, Dimitris Nikolos. 281-284 [doi]
• An Efficient Test Vector Ordering Method for Low Power TestingXrysovalantis Kavousianos, Dimitris Bakalis, Maciej Bellos, Dimitris Nikolos. 285-288 [doi]
• Concurrent Pseudo-Exhaustive Testing of Combinational VLSI CircuitsBassam Shaer. 289-290 [doi]
• CMOS Analog Programmable Logic ArrayChandrasekar Rajagopal, Adrián Núñez-Aldana. 291-292 [doi]
• Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications Sotirios Matakias, Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni. 293-296 [doi]
• A 64-bit Decimal Floating-Point AdderJohn D. Thompson, Nandini Karra, Michael J. Schulte. 297-298 [doi]
• Parallel Programmable Finite Field GF(2m) MultipliersNick Iliev, James E. Stine, Nathan Jachimiec. 299-302 [doi]
• Autonomous Buffer Controller Design for Concurrent Execution in Block Level Pipelined DataflowMagesh Sadasivam, Sangjin Hong. 303-304 [doi]
• Compiler-Directed Data Cache Leakage ReductionWei Zhang 0002. 305-306 [doi]
• FPGA Placement and Routing Using Particle Swarm OptimizationVenu G. Gudise, Ganesh K. Venayagamoorthy. 307-308 [doi]
• A Reconfigurable Memory Management Core for Java ApplicationsAbdel Ejnioui, Abdelkader Rhiati. 309-312 [doi]
• A Technique for Energy versus Quality of Service Trade-Off for MPEG-2 DecoderKrishnan Srinivasan, Vijay Ramamurthi, Karam S. Chatha. 313-316 [doi]
• FSEL - Selective Predicated Execution for a Configurable DSP CoreChristian Panis, Ulrich Hirnschrott, Andreas Krall, Gunther Laure, Wolfgang Lazian, Jari Nurmi. 317-320 [doi]
• A Spiking Recurrent Neural NetworkYuan Li, John G. Harris. 321-322 [doi]