Table of Contents

• Gyrator-C Based Bandpass Filter with Improved Dynamic Range for Fully Integrated RF Front-EndLakshmi N. S, Bhaskar M. 1-5 [doi]
• Replica-Based Low Drop-Out Voltage Regulator with Assistant Power Transistors for Digital VLSI SystemsYang Nan, Chenchang Zhan, Guanhua Wang, Linjun He, Han Li. 6-9 [doi]
• Area Efficient NMOS Based Positive and Negative Voltage MultiplierVikas Rana. 10-15 [doi]
• Achieving Low Power Classification with Classifier EnsembleFanglei Hu, Min Zhang, Hailong Jiao. 16-21 [doi]
• A Power-Efficient Hybrid Architecture Design for Image Recognition Using CNNsJinhang Choi, Srivatsa Rangachar Srinivasa, Yasuki Tanabe, Jack Sampson, Vijaykrishnan Narayanan. 22-27 [doi]
• Towards Budget-Driven Hardware Optimization for Deep Convolutional Neural Networks Using Stochastic ComputingZhe Li 0001, Ji Li 0006, Ao Ren, Caiwen Ding, Jeffrey Draper, Qinru Qiu, Bo Yuan 0001, Yanzhi Wang. 28-33 [doi]
• Fast Heuristics for Near-Optimal Signal Restoration in Post-Silicon ValidationXiaobang Liu, Ranga Vemuri. 34-39 [doi]
• PGIREM: Reliability-Constrained IR Drop Minimization and Electromigration Assessment of VLSI Power Grid Networks Using Cooperative CoevolutionSukanta Dey, Satyabrata Dash, Sukumar Nandi, Gaurav Trivedi. 40-45 [doi]
• Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor AlgorithmAnkit Jindal, Binod Kumar 0001, Nitish Jindal, Masahiro Fujita, Virendra Singh. 46-51 [doi]
• Application Specific Networks-on-Chip Synthesis: An Energy Efficient ApproachSomayeh Kashi, Ahmad Patooghy, Dara Rahmatiy, Mahdi Fazeli, Michel A. Kinsy. 52-57 [doi]
• Accurate Models for Optimizing Tapered Microchannel Heat Sinks in 3D ICsLeslie Hwang, Beomjin Kwon, Martin D. F. Wong. 58-63 [doi]
• Designing and Benchmarking of Double-Row Height Standard CellsYu-Xiang Chiang, Cheng-Wei Tai, Shang-Rong Fang, Kai-Chun Peng, Yuan-Dar Chung, Jin-Kai Yang, Rung-Bin Lin. 64-69 [doi]
• A Dual-Threshold Scheme Along with Security Reinforcement for Energy Efficient Nonvolatile ProcessorsDongqin Zhou, Keni Qiu, Yuanchao Xu, Xin Shi, Yongpan Liu. 70-75 [doi]
• A Comprehensive Electro-Optical Model for Silicon Photonic SwitchesXuanqi Chen, Zhifei Wang, Yi-Shing Chang, Jiang Xu 0001, Peng Yang 0003, Zhehui Wang, Luan H. K. Duong. 76-81 [doi]
• CMOS Gates with Second FunctionJan Nevoral, Richard Ruzicka, Vaclav Simek. 82-87 [doi]
• TDC: Tagless DRAM CacheS. R. Swamy Saranam, Madhu Mutyam. 88-93 [doi]
• CT-Cache: Compressed Tag-Driven Cache ArchitectureHaeyoon Cho, Joonho Kong, Arslan Munir, Naresh Kumar Giri. 94-99 [doi]
• High Bandwidth Off-Chip Memory Access Through Hybrid Switching and Inter-Chip Wireless LinksSri Harsha Gade, Hemanta Kumar Mondal, Sujay Deb. 100-105 [doi]
• Investigating Reliability and Security of Integrated Circuits and SystemsQiaoyan Yu, Zhiming Zhang, Jaya Dofe. 106-111 [doi]
• Reliability and Security in Non-volatile Processors, Two Sides of the Same CoinPatrick Cronin, Chengmo Yang, Yongpan Liu. 112-117 [doi]
• A Short Survey at the Intersection of Reliability and Security in Processor Architecture DesignsLake Bu, Miguel Mark, Michel A. Kinsy. 118-123 [doi]
• Can Soft Errors be Handled Securely?Senwen Kan, Jennifer Dworak. 124-129 [doi]
• BD-NET: A Multiplication-Less DNN with Binarized Depthwise Separable ConvolutionZhezhi He, Shaahin Angizi, Adnan Siraj Rakin, Deliang Fan. 130-135 [doi]
• TaiJiNet: Towards Partial Binarized Convolutional Neural Network for Embedded SystemsYingjian Ling, Kan Zhong, Yunsong Wu, Duo Liu, Jinting Ren, Renping Liu, Moming Duan, Weichen Liu, Liang Liang 0002. 136-141 [doi]
• An ECC-Free MLC STT-RAM Based Approximate Memory Design for Multimedia ApplicationsZihao Liu, Tao Liu, Jie Guo 0002, Nansong Wu, Wujie Wen. 142-147 [doi]
• Robust Timing Attack Countermeasure on Virtual HardwareKai Yang, Jungmin Park, Mark Tehranipoor, Swarup Bhunia. 148-153 [doi]
• Towards Theoretical Cost Limit of Stochastic Number Generators for Stochastic ComputingMeng Yang, Bingzhe Li, David J. Lilja, Bo Yuan 0001, Weikang Qian. 154-159 [doi]
• Fully-on-Chip Digitally Assisted LDO Regulator with Improved Regulation and Transient ResponsesHan Li, Chenchang Zhan, Ning Zhang. 160-163 [doi]
• An Asynchronous Analog to Digital Converter for Surveillance Camera ApplicationsR. K. Siddharth, Sunil R., Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni. 164-169 [doi]
• An Integrated MaxFit Genetic Algorithm-SPICE Framework for 2-Stage Op-Amp Design AutomationHarsha M. V., B. P. Harish. 170-174 [doi]
• Mismatch Resilient 3.5-Bit MDAC with MCS-CFCSSatyajit Mohapatra, Hari Shanker Gupta, Nihar Ranjan Mohapatra. 175-180 [doi]
• Design of Low Power SAR ADC Using Clock RetimingJalaja S, Vijaya Prakash A. M. 181-186 [doi]
• A 375 nA Input Off Current Schmitt Triger LDO for Energy Harvesting IoT SensorsKoichiro Ishibashi, Shiho Takahashi. 187-190 [doi]
• Precise Duty Cycle Variation Detection and Self-Calibration System for High-Speed Data LinksKaren Khachikyan, Abraham Balabanyan, Hrachya Gumroyan. 191-196 [doi]
• Parametric Circuit Optimization with Reinforcement LearningChangcheng Tang, Zuochang Ye, Yan Wang. 197-202 [doi]
• End-to-End Industrial Study of RetimingCunxi Yu, Chau-Chin Huang, Gi-Joon Nam, Mihir Choudhury, Victor N. Kravets, Andrew Sullivan, Maciej J. Ciesielski, Giovanni De Micheli. 203-208 [doi]
• Communication-Aware Module Placement for Power Reduction in Large FPGA DesignsKalindu Herath, Alok Prakash, Udaree Kanewala, Thambipillai Srikanthan. 209-214 [doi]
• A Novel Mixed-Size Fixed-Outline Floorplacement AlgorithmQian Chen, Sheqin Dong. 215-219 [doi]
• ARCHVerifyr: An Embedded Software-Driven Approach for Architecture VerificationTomas Grimm, Djones Lettnin, Michael Hübner. 220-225 [doi]
• High-Average and Guaranteed Performance for Wireless Networks-on-Chip ArchitecturesMohammad Baharloo, Ahmad Khonsari, Pouya Shiri, Iman Namdari, Dara Rahmati. 226-231 [doi]
• Hardware Implementation of Reconfigurable Separable ConvolutionLei Rao, Bin Zhang 0022, Jizhong Zhao. 232-237 [doi]
• Low Overhead Online Checkpoint for Intermittently Powered Non-volatile FPGAsXinyi Zhang, Clay Patterson, Yongpan Liu, Chengmo Yang, Chun Jason Xue, Jingtong Hu. 238-244 [doi]
• Pixel-Parallel Architecture for Neuromorphic Smart Image Sensor with Visual AttentionMd Jubaer Hossain Pantho, Pankaj Bhowmik, Christophe Bobda. 245-250 [doi]
• Lightweight ASIC Implementation of AEGIS-128Anubhab Baksi, Vikramkumar Pudi, Swagata Mandal, Anupam Chattopadhyay. 251-256 [doi]
• Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate ArraysChia-Cheng Wu, Kung-Han Ho, Juinn-Dar Huang, Chun-Yao Wang. 257-262 [doi]
• MRAM-on-FDSOI Integration: A Bit-Cell PerspectiveHao Cai, You Wang, Wang Kang, Lirida A. B. Naviner, Xinning Liu, Jun Yang, Weisheng Zhao. 263-268 [doi]
• High Performance Ternary Multiplier Using CNTFETSubhendu Kumar Sahoo, Krishna Dhoot, Rasmita Sahoo. 269-274 [doi]
• A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAMLiuyang Zhang, Wang Kang, Hao Cai, Peng Ouyang, Lionel Torres, Youguang Zhang, Aida Todri-Sanial, Weisheng Zhao. 275-280 [doi]
• Biosensing Performance Optimization of DMFET for Fully Filled and Partially Filled CavityAnkita Porwal, Chitrakant Sahu. 281-286 [doi]
• A Dynamic Resource Allocation Strategy for NoC Based Multicore Systems with Permanent FaultsSuraj Paul, Navonil Chatterjee, Prasun Ghosal. 287-292 [doi]
• Floorplanning in Graphene Nanoribbon (GNR) Based CircuitsSubrata Das, Debesh Kumar Das. 293-298 [doi]
• Generating Safety Guidance for Medical Injection with Three-Compartment Pharmacokinetics ModelCunxi Yu, Heinz Riener, Francesca Stradolini, Giovanni De Micheli. 299-304 [doi]
• A Novel Approach for Nearest Neighbor Realization of 2D Quantum CircuitsAnirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman. 305-310 [doi]
• A Hardware-Efficient Implementation of CLOC for On-chip Authenticated EncryptionMahmoud A. Elmohr, Sachin Kumar, Mustafa Khairallah, Anupam Chattopadhyay. 311-315 [doi]
• 0.9 to 2.5 GHz Sub-Sampling Receiver Architecture for Dynamically Reconfigurable SDRAjinkya Kale, Johannes Sturm, Vijaya Sankara Rao Pasupureddi. 316-320 [doi]
• Hardware Obfuscation Using Strong PUFsSoroush Khaleghi, Wenjing Rao. 321-326 [doi]
• Multi-block APUF with 2-Level Voltage SupplyYunxi Guo, Timothy Dee, Akhilesh Tyagi. 327-332 [doi]
• Write Energy Optimization for STT-MRAM Cache with Data Pattern CharacterizationBi-Wu, Xiaolong Zhang, Yuanqing Cheng, Zhaohao Wang, Dijun Liu, Youguang Zhang, Weisheng Zhao. 333-338 [doi]
• Time Stamp Based Scheduling for Energy Harvesting Systems with Hybrid Nonvolatile Hardware SupportXin Shi, Tongda Wu, Keni Qiu, Huazhong Yang, Yongpan Liu. 339-344 [doi]
• EETD: An Energy Efficient Design for Runtime Hardware Trojan Detection in Untrusted Network-on-ChipMubashir Hussain, Amin Malekpour, Hui Guo, Sri Parameswaran. 345-350 [doi]
• Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex MultipliersAlireza Mahzoon, Daniel Große, Rolf Drechsler. 351-356 [doi]
• Enhancing Lifetime of PCM-Based Main Memory with Efficient Recovery of Stuck-at FaultsMarjan Asadinia, Christophe Bobda. 357-362 [doi]
• Guessing Your PIN Right: Unlocking Smartphones with Publicly Available Sensor DataDavid Berend, Bernhard Jungk, Shivam Bhasin. 363-368 [doi]
• Synthesis, Technology Mapping and Optimization for Emerging TechnologiesDebjyoti Bhattacharjee, Anupam Chattopadhyay. 369-374 [doi]
• Logic Synthesis for In-memory Computing Using Resistive MemoriesSaeideh Shirinzadeh, Rolf Drechsler. 375-380 [doi]
• Minimalistic Perspective to Public Key Implementations on FPGADebapriya Basu Roy, Debdeep Mukhopadhyay. 381-386 [doi]
• Development of High-Stability, Low-Leakage 6Tr-SRAM with Single Data Line and Single Power Supply Using SOTB ProcessShin Miyamoto, Nobuaki Kobayashi. 387-392 [doi]
• Exploiting Principle of Moving Target Defense to Secure FPGA SystemsZhiming Zhang, Qiaoyan Yu. 393-398 [doi]
• A Highly Flexible Lightweight and High Speed True Random Number Generator on FPGAFaqiang Mei, Lei Zhang, Chongyan Gu, Yuan Cao, Chenghua Wang, Weiqiang Liu. 399-404 [doi]
• LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware ProtectionHadi Mardani Kamali, Kimia Zamiri Azar, Kris Gaj, Houman Homayoun, Avesta Sasan. 405-410 [doi]
• ArtiFact: Architecture and CAD Flow for Efficient Formal Verification of SoC Security PoliciesAtul Prasad Deb Nath, Swarup Bhunia, Sandip Ray. 411-416 [doi]
• Identifying Lithography Weak-Points of Standard Cells with Partial Pattern MatchingYongfu Li, I-Lun Tseng, Zhao Chuan Lee, Valerio Perez, Vikas Tripathi, Yoong Seang Jonathan Ong. 417-422 [doi]
• Feature Based Coverage Analysis of AMS CircuitsAntara Ain, Akshay Mambakam, Pallab Dasgupta. 423-428 [doi]
• SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGARyutaro Doi, Masanori Hashimoto. 429-434 [doi]
• RRAM Based Buffer Design for Energy Efficient CNN AcceleratorKaiyuan Guo, Jincheng Yu, Xuefei Ning, Yiming Hu, Yu Wang 0002, Huazhong Yang. 435-440 [doi]
• A Mixed-Mode Neuron with On-chip Tunability for Generic Use in Memristive Neuromorphic SystemsSagarvarma Sayyaparaju, Ryan Weiss, Garrett S. Rose. 441-446 [doi]
• Harnessing Emerging Technology for Compute-in-Memory SupportNicholas Jao, Akshay Krishna Ramanathan, Srivatsa Rangachar Srinivasa, Sumitha George, John Sampson, Vijaykrishnan Narayanan. 447-452 [doi]
• 91dB Dynamic Range 9.5nW Low Pass Filter for Bio-Medical ApplicationsM. K. Jayaram Reddy, Sreenivasulu Polineni, Laxminidhi Tonse. 453-457 [doi]
• A Low Power, High Gain Semi-Floating Gate Amplifier for Resonating Sensors Front-EndLuca Marchetti, Yngvar Berg, Mehdi Azadmehr. 458-463 [doi]
• A High-Efficient Current-Mode PWM DC-DC Buck Converter Using Dynamic Frequency ScalingAnkit Rehani, Sujay Deb, Pydi Ganga Bahubalindruni, Bhavin Odedara, Srikanth Bojja. 464-469 [doi]
• ReRise: An Adversarial Example Restoration System for Neuromorphic Computing SecurityChenchen Liu, Qide Dong, Fuxun Yu, Xiang Chen 0010. 470-475 [doi]
• MAT: A Multi-strength Adversarial Training Method to Mitigate Adversarial AttacksChang Song, Hsin-Pai Cheng, Huanrui Yang, Sicheng Li, Chunpeng Wu, Qing Wu, Yiran Chen, Hai Li. 476-481 [doi]
• Hu-Fu: Hardware and Software Collaborative Attack Framework Against Neural NetworksWenshuo Li, Jincheng Yu, Xuefei Ning, Pengjun Wang, Qi Wei 0001, Yu Wang, Huazhong Yang. 482-487 [doi]
• Sparse VLSI Layout Feature Extraction: A Dictionary Learning ApproachHao Geng, Haoyu Yang, Bei Yu, Xingquan Li, Xuan Zeng 0001. 488-493 [doi]
• Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic ResponsesAtsushi Takahashi 0001, Shimpei Sato, Hiroki Ogura, Yu-Min Sung, Ting-Chi Wang. 494-497 [doi]
• Recent Research and Challenges in Multiple Patterning Layout DecompositionIris Hui-Ru Jiang, Hua-Yu Chang. 498-499 [doi]
• Guiding Template-Induced Design Challenges in DSA-MP LithographyShao-Yun Fang, Kuo-Hao Wu. 500-502 [doi]
• FPAP: A Folded Architecture for Efficient Computing of Convolutional Neural NetworksYizhi Wang, Jun Lin, Zhongfeng Wang. 503-508 [doi]
• Hyperdrive: A Systolically Scalable Binary-Weight CNN Inference Engine for mW IoT End-NodesRenzo Andri, Lukas Cavigelli, Davide Rossi, Luca Benini. 509-515 [doi]
• An Optimized Architecture For Decomposed Convolutional Neural NetworksFangxuan Sun, Jun Lin, Zhongfeng Wang. 516-521 [doi]
• Interconnect Delay Analysis for RRAM Crossbar Based FPGAMasanori Hashimoto, Yuki Nakazawa, Ryutaro Doi, Jaehoon Yu. 522-527 [doi]
• Enhancing the Robustness of Deep Neural Networks from "Smart" CompressionTao Liu, Zihao Liu, Qi Liu, Wujie Wen. 528-532 [doi]
• Accelerating Low Bit-Width Deep Convolution Neural Network in MRAMZhezhi He, Shaahin Angizi, Deliang Fan. 533-538 [doi]
• Emerging Neuromorphic Computing Paradigms Exploring Magnetic SkyrmionsSai Li, Wang Kang, Xing Chen, Jinyu Bai, Biao Pan, Youguang Zhang, Weisheng Zhao. 539-544 [doi]
• Security-Driven Task Scheduling for Multiprocessor System-on-Chips with Performance ConstraintsNan Wang 0003, Manting Yao, DongXu Jiang, Song Chen 0001, Yu Zhu. 545-550 [doi]
• A Hardware Monitor to Protect Linux System CallsGeorge Provelengios, Arman Pouraghily, Russell Tessier, Tilman Wolf. 551-556 [doi]
• Towards Dynamic Execution Environment for System Security Protection Against Hardware FlawsKenneth Schmitz, Oliver Keszöcze, Jurij Schmidt, Daniel Große, Rolf Drechsler. 557-562 [doi]
• A Fast and Effective Memristor-Based Method for Finding Approximate Eigenvalues and Eigenvectors of Non-negative MatricesChenghong Wang, Zeinab S. Jalali, Caiwen Ding, Yanzhi Wang, Sucheta Soundarajan. 563-568 [doi]
• A Low-Power and Small-Area Multiplier for Accuracy-Scalable Approximate ComputingHiroyuki Baba, Tongxin Yang, Masahiro Inoue, Kaori Tajima, Tomoaki Ukezono, Toshinori Sato. 569-574 [doi]
• A Hardware/Software Co-design Method for Approximate Semi-Supervised K-Means ClusteringPengfei Huang Huang, Chenghua Wang, Ruizhe Ma, Weiqiang Liu, Fabrizio Lombardi. 575-580 [doi]
• Robustness for Smart Cyber Physical Systems and Internet-of-Things: From Adaptive Robustness Methods to Reliability and Security for Machine LearningFlorian Kriebel, Semeen Rehman, Muhammad Abdullah Hanif, Faiq Khalid, Muhammad Shafique 0001. 581-586 [doi]
• On How to Efficiently Implement Deep Learning Algorithms on PYNQ PlatformLuca Stornaiuolo, Marco D. Santambrogio, Donatella Sciuto. 587-590 [doi]
• Enabling Reliable High Throughput On-chip Wireless Communication for Many Core ArchitecturesSri Harsha Gade, Mitali Sinha, Sidhartha Sankar Rout, Sujay Deb. 591-596 [doi]
• Predicting the Tolerance of Extreme Electromagnetic Interference on MOSFETsNishchay H. Sule, Troy Powell, Sameer Hemmady, Payman Zarkesh-Ha. 597-601 [doi]
• Enhancing Observability for Post-Silicon Debug with On-chip Communication MonitorsYuting Cao, Hernan M. Palombo, Sandip Ray, Hao Zheng. 602-607 [doi]
• Performance Enhancement of Split Length Compensated Operational AmplifiersDonel Anto, Abhijeet D. Taralkar, Kumar Y. B. Nithin, M. H. Vasantha. 608-613 [doi]
• Design-Based Fingerprinting Using Side-Channel Power Analysis for Protection Against IC PiracyJames Shey, Naghmeh Karimi, Ryan Robucci, Chintan Patel. 614-619 [doi]
• PPAP and iPPAP: PLL-Based Protection Against Physical AttacksPrasanna Ravi, Shivam Bhasin, Jakub Breier, Anupam Chattopadhyay. 620-625 [doi]
• Mystic: Mystifying IP Cores Using an Always-ON FSM Obfuscation MethodAhmad Patooghy, Ehsan Aerabi, Hamidreza Rezaei, Miguel Mark, Mahdi Fazeli, Michel A. Kinsy. 626-631 [doi]
• FPGA-Based Controllers for Compact Low Power Refreshable Braille DisplaySuman Adhepalli Muralikrishnan, Pulkit Sapra, Saurabh Agrawal, Piyush Chanana, M. Balakrishnan, P. V. M. Rao. 632-637 [doi]
• Very Large-Scale and Node-Heavy Graph Analytics with Heterogeneous FPGA+CPU Computing PlatformYu Zou, Mingjie Lin. 638-643 [doi]
• On-chip Data Security Against Untrustworthy Software and Hardware IPs in Embedded SystemsSreeCharan Gundabolu, Xiaofang Wang. 644-649 [doi]
• Design Automation and Test for Flow-Based Biochips: Past Successes and Future ChallengesTsung-Yi Ho. 650-654 [doi]
• Multi-target Many-Reactant Sample Preparation for Reactant Minimization on Microfluidic BiochipsYung-Chun Lei, Tien-Kuo Lin, Juinn-Dar Huang. 655-659 [doi]
• More Effective Randomly-Designed MicrofluidicsWeiqing Ji, Tsung-Yi Ho, Hailong Yao. 660-665 [doi]
• Accelerating Simulation of Particle Trajectories in Microfluidic Devices by Constructing a Cloud DatabaseJunchao Wang, Lingxuan Fu, Liyang Yu, Xiwei Huang, Philip Brisk, William H. Grover. 666-671 [doi]
• PUF-Based Secure Test Wrapper for SoC TestingSudeendra Kumar K, Saurabh Seth, Sauvagya Ranjan Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, Kamalakanta Mahapatra. 672-677 [doi]
• Detection of Sequential Trojans in Embedded System Designs Without Scan ChainsPranav Dharmadhikari, Akhilesh Raju, Ranga Vemuri. 678-683 [doi]
• Designing for Security Within and Between IoT DevicesMike Borowczak, Rafer Cooley, Shaya Wolf. 684-689 [doi]
• A Two-Tiered Heterogeneous and Reconfigurable Application Processor for Future Internet of ThingsPrasanna Kansakar, Arslan Munir. 690-696 [doi]
• Solar Cell Based Physically Unclonable Function for Cybersecurity in IoT DevicesS. Dinesh Kumar, Carson Labrado, Riasad Badhan, Himanshu Thapliyal, Vijay Singh. 697-702 [doi]
• Designing Scalable Hybrid Wireless NoC for GPGPUsHui Zhao, Xianwei Cheng, Saraju P. Mohanty, Juan Fang. 703-708 [doi]
• Functional Obfuscation of DSP Cores Using Robust Logic Locking and EncryptionAnirban Sengupta, Saraju P. Mohanty. 709-713 [doi]
• Timing Macro Modeling for Efficient Hierarchical Timing AnalysisIris Hui-Ru Jiang, Pei-Yu Lee. 714 [doi]
• Timing with Virtual Signal Synchronization for Circuit Performance and Netlist SecurityGrace Li Zhang, Bing Li 0005, Ulf Schlichtmann. 715-718 [doi]
• Realizing Closed-Loop, Online Tuning and Control for Configurable-Cache Embedded Systems: Progress and ChallengesIslam Badreldin, Ann Gordon-Ross, Tosiron Adegbija, Mohamad Hammam Alsafrjalani. 719-725 [doi]
• An FPGA-Based Brain Computer Interfacing Using Compressive Sensing and Machine LearningRitu Ranjan Shrivastwa, Vikramkumar Pudi, Anupam Chattopadhyay. 726-731 [doi]
• Obfuscation of Fault Secured DSP Design Through Hybrid TransformationAnirban Sengupta, Shubha Neema, Pallabi Sarkar, Sri Harsha P, Saraju P. Mohanty, Mrinal Kanti Naskar. 732-737 [doi]
• Run Time Mitigation of Performance Degradation Hardware Trojan Attacks in Network on ChipManoj Kumar JYV, Ayas Kanta Swain, Sudeendra Kumar K, Sauvagya Ranjan Sahoo, Kamalakanta Mahapatra. 738-743 [doi]
• Exploration on Routing Configuration of HNoC with Reasonable Energy ConsumptionJuan Fang, Zeqing Chang, Yanjin Cheng, Hui Zhao. 744-749 [doi]
• Nonvolatile Memory and Computing Using Emerging Ferroelectric TransistorsXueqing Li, Longqiang Lai. 750-755 [doi]
• Software Support for Heterogeneous ComputingSiqi Wang, Alok Prakash, Tulika Mitra. 756-762 [doi]
• Predictive Modeling for CPU, GPU, and FPGA Performance and Power Consumption: A SurveyKenneth O'Neal, Philip Brisk. 763-768 [doi]