Abstract is missing.
- Response time schedulability analysis for hard real-time systems accounting DVFS latency on heterogeneous cluster-based platformEduardo Valentin, Mario Salvatierra, Rosiane de Freitas, Raimundo S. Barreto. 1-8 [doi]
- Inferring custom architectures from OpenCLKrzysztof Kepa, Ritesh Soni, Peter M. Athanas. 9-16 [doi]
- ABeeMap: A mapping algorithm based on multi-objective Artificial Bee ColonyViviane Lucy Santos de Souza, Abel G. Silva-Filho, V. C. Wanderely. 17-24 [doi]
- Efficient parallelization of the Discrete Wavelet Transform algorithm using memory-oblivious optimizationsAnastasis Keliris, Vasilis Dimitsas, Olympia Kremmyda, Dimitris Gizopoulos, Michail Maniatakos. 25-32 [doi]
- Calculation of worst-case execution time for multicore processors using deterministic executionHamid Mushtaq, Zaid Al-Ars, Koen Bertels. 33-39 [doi]
- An unconventional computing technique for ultra-fast and ultra-low power data miningVincent Canals, Antoni Morro, Antoni Oliver, Miquel Lleo Alomar, Josep L. Rosselló. 40-46 [doi]
- Tejas: A java based versatile micro-architectural simulatorSmruti R. Sarangi, Rajshekar Kalayappan, Prathmesh Kallurkar, Seep Goel, Eldhose Peter. 47-54 [doi]
- Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuitSoundous Chairat, Edith Beigné, Marc Belleville. 55-62 [doi]
- Energy management via PI control for data parallel applications with throughput constraintsAnca Mariana Molnos, Warody Lombardi, Diego Puschini, Julien Mottin, Suzanne Lesecq, Arnaud Tonda. 63-70 [doi]
- VLSI architecture design and implementation of a LDPC encoder for the IEEE 802.22 WRAN standardNelson Alves Ferreira Neto, Joaquim Ranyere S. de Oliveira, Wagner Luiz Alves de Oliveira, Joao Carlos N. Bittencourt. 71-76 [doi]
- Dynamic current reduction of CMOS digital circuits through design and process optimizationJordan Innocenti, Loïc Welter, Nicolas Borrel, Franck Julien, Jean Michel Portal, Jacques Sonzogni, Laurent Lopez, Pascal Masson, Stephan Niel, Philippe Dreux, Julia Castellan. 77-81 [doi]
- Unified Power Format (UPF) methodology in a vendor independent flowEmilie Garat, David Coriat, Edith Beigné, Leandro Stefanazzi. 82-88 [doi]
- Asynchronous sub-threshold ultra-low power processorRon Diamant, Ran Ginosar, Christos P. Sotiriou. 89-96 [doi]
- Constructing stability-based clock gating with hierarchical clusteringBao Le, Djordje Maksimovic, Dipanjan Sengupta, Erhan Ergin, Ryan Berryhill, Andreas G. Veneris. 97-102 [doi]
- Adaptive energy minimization of embedded heterogeneous systems using regression-based learningSheng Yang, Rishad A. Shafik, Geoff V. Merrett, Edward A. Stott, Joshua M. Levine, James Davis, Bashir M. Al-Hashimi. 103-110 [doi]
- Evaluation and mitigation of aging effects on a digital on-chip voltage and temperature sensorMauricio Altieri, Suzanne Lesecq, Diego Puschini, Olivier Héron, Edith Beigné, Jorge Rodas. 111-117 [doi]
- Exploration of technology parameter values of integrated circuit technologiesRodrigo Fonseca Rocha Soares, Frank Sill Torres, Dirk Timmermann. 118-125 [doi]
- Frequency-domain modeling of ground bounce and substrate noise for synchronous and GALS systemsMilan Babic, Xin Fan, Milos Krstic. 126-131 [doi]
- Better-than-voltage scaling energy reduction in approximate SRAMs via bit dropping and bit reuseFabio Frustaci, David Blaauw, Dennis Sylvester, Massimo Alioto. 132-139 [doi]
- A versatile and reliable glitch filter for clocksRobert Najvirt, Andreas Steininger. 140-147 [doi]
- Energy-efficient Level Shifter topologyRoger Llanos, Diego Sousa, Marco Terres, Guilherme Bontorin, Ricardo Reis, Marcelo de Oliveira Johann. 148-151 [doi]
- Energy efficiency of Zipf traffic distributions within Facebook's data center fabric architectureLisa J. K. Durbeck, Joseph G. Tront, Nicholas J. Macias. 152-160 [doi]
- Energy-aware mapping for dependable virtual networksVictor Lira, Eduardo Tavares. 161-168 [doi]
- Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTsSidinei Ghissoni, Eduardo Costa, Ricardo Reis. 169-176 [doi]
- Combining Pel Decimation with Partial Distortion Elimination to increase SAD energy efficiencyIsmael Seidel, André Beims Bräscher, José Luís Güntzel. 177-184 [doi]
- Wideband dynamic voltage sensing mechanism for EH systemsK. Gao, Y. Xu, D. Shang, F. Xia, A. Yakovlev. 185-192 [doi]