Table of Contents

• Broker Fault Recovery for a Multiprocessor System-an-Chip MiddlewareAnderson R. P. Domingues, Jean Carlo Hamerski, Alexandre M. Amory. 1-6 [doi]
• A Novel Limiter with Application in Crest Factor Reduction Techniques for Wireless CommunicationsLeandro Dias da Silva, Eduardo Gonçalves de Lima. 1-6 [doi]
• Automatic Optimization of Robust Analog CMOS ICs: An Interactive Genetic Algorithm Driven by Human KnowledgeRodrigo Alves De Lima Moreto, Carlos Eduardo Thomaz, Salvador Pinillos Gimenez. 1-6 [doi]
• Improving Software Productivity and Performance Through a Transparent SIMD ExecutionMichael Guilherme Jordan, Tiago Knorst, Mateus Beck Rutzig. 1-6 [doi]
• Exploiting Partial Distortion Elimination in the Sum of Absolute Differences for Energy-Efficient HEVC Integer Motion EstimationBrunno Abreu, Gustavo M. Santana, Mateus Grellert, Guilherme Paim, Leandro M. G. Rocha, Eduardo A. C. da Costa, Sergio Bampi. 1-6 [doi]
• 16NM 6T and 8T CMOS SRAM Cell Robustness Against Process Variability and Aging EffectsRoberto B. Almeida, Paulo F. Butzen, Cristina Meinhardt. 1-6 [doi]
• Hybrid Memory Cube in Embedded SystemsCarlos Michel Betemps, Maurício Lima Pilla, Bruno Zatt. 1-6 [doi]
• Bandwidth Efficient Gaussian Minimum Frequency-Shift Keying Approach for Software Defined RadioLucas C. Galvao, Candice Müller, Maria Cristina Felippetto de Castro, Fernando. C. C. De Castro, Kayol S. Mayer. 1-4 [doi]
• A Differential Low Power Wake-Up Circuit Based on Systematic Offset for RFID ApplicationsRafael Cantalice, Daniel Barcelos, Fabricio Mattos, Fernando Paixão Cortes. 1-6 [doi]
• A Programmable Gain Amplifier for Load Demodulation Channel in an NFC Reader ChipTarciso A. Martins, Julio Saldana, Wilhelmus A. M. Van Noije. 1-6 [doi]
• Low Power Bulk-Driven OTA Design Optimization Using Cuckoo Search AlgorithmAnderson Fortes, Luiz A. Da Silva, Alessandro Girardi. 1-7 [doi]
• Comparative Analysis of Inference Errors in a Neural Network Implemented in SRAM-Based FPGA Induced by Neutron Irradiation and Fault Injection MethodsFabio Benevenuti, Fabiano Libano, Vincent Pouget, Fernanda Lima Kastensmidt, Paolo Rech. 1-6 [doi]
• Improving Energy Efficiency on Partially Reversible Pipelined QCA CircuitsMarco A. Ribeiro, Iago A. Carvalho, Jeferson F. Chaves, Omar P. Vilela Neto. 1-6 [doi]
• Hardware-Oriented Wedgelet Evaluation Skip for DMM-1 in 3D-HEVCGustavo Sanchez, Mário Saldanha, Luciano Volcan Agostini, César A. M. Marcon. 1-5 [doi]
• A -40 to 250°C Triple Modular Redundancy Temperature Sensor for Turbofan EnginesPietro Maris Ferreira, Martin Schaeffer, Adel Mezaour, Olivier Petit, Caroline Lelandais-Perrault, Gerald Charbonnier. 1-6 [doi]
• A Charge-Sharing Bandpass Filter Topology with Boosted Q-Factor in 40-NM CMOSFilipe D. Baumgratz, Sandro B. Ferreira, Michiel Steyaert, Sergio Bampi, Filip Tavernier. 1-6 [doi]
• Heavy Ion Microbeam Experimental Study of ASET on a Full-Custom CMOS OpAmpA. Fontana, S. M. Pazos, F. L. Aguirre, F. Palumbo, Nahuel Vega, N. A. Muller, E. de la Fourniere, Mario Debray. 1-5 [doi]
• Low-Power and High-Throughput Architecture for 3D-HEVC Depth Modeling Mode 4Mariana Ucker, Vladimir Afonso, Luan Audibert, Altamiro Amadeu Susin, Bruno Zatt, Marcelo Schiavon Porto, Luciano Volcan Agostini. 1-6 [doi]
• Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis EvaluationWalter L. Neto, Vinicius Neves Possani, Felipe S. Marranghello, Jody Maick Matos, André Inácio Reis, Renato P. Ribas. 1-6 [doi]
• High Throughput Multiplierless Architecture for VP9 Fractional Motion EstimationJones Goebel, Lucas Agostini, Luciano Volcan Agostini, Bruno Zatt, Marcelo Schiavon Porto. 1-6 [doi]
• Operational Amplifier Performance Degradation and Time-to-Failure due to ElectromigrationR. O. Nunes, R. L. de Orio. 1-6 [doi]
• A Design Patterns-Based Middleware for Multiprocessor Systems-on-ChipJean Carlo Hamerski, Geancarlo Abich, Ricardo Reis, Luciano Ost, Alexandre M. Amory. 1-6 [doi]
• Efficient Hardware Implementation of the Fast Hybrid Morphological Reconstruction AlgorithmOscar Anacona-Mosquera, Felipe R. G. Cabral, Renato Coral Sampaio, George Teodoro, Ricardo P. Jacobi, Carlos H. Llanos. 1-6 [doi]
• Multi-Terminal PiezoMOSFET Sensor for Stress Measurements in SiliconJose L. Ramirez, Fabiano Fruett. 1-6 [doi]
• An Adaptive Closed-Loop Verification Approach in UVM-SystemC for AMS CircuitsJeferson Santos Barros, Victor Hugo Schulz, Djones Vinicius Lettnin. 1-6 [doi]
• Secure Environment Architecture for MPSoCsBruno Scherer Oliveira, Henrique Martins Medina, Anderson C. Sant'Ana, Fernando Gehm Moraes. 1-6 [doi]
• A Power-Efficient and High-Throughput Hardware Design for 3D-HEVC Disparity EstimationMurilo R. Perleberg, Vladimir Afonso, Ruhan Conceicao, Altamiro Amadeu Susin, Luciano Volcan Agostini, Bruno Zatt, Marcelo Schiavon Porto. 1-6 [doi]
• BANCS: Bidirectional Alternating Nanomagnetic Clocking SchemeRuan Evangelista Formigoni, Omar P. Vilela Neto, José Augusto Miranda Nacif. 1-6 [doi]
• An FPGA-Based RFID Baseband Processor Using a RISC-V PlatformPedro J. A. Ishimaru, Antonyus P. A. Ferreira, Vanessa O. Ogg, Cecil Accetti R. de A. Melo, Edna Natividade da Silva Barros. 1-6 [doi]
• Enhancing Multi-Threaded Legalization Through k-d Tree Circuit PartitioningSheiny Fabre, José Luís Güntzel, Laércio Lima Pilla, Renan Netto, Tiago Fontana, Vinicius S. Livramento. 1-6 [doi]
• Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient TemplateFelipe A. Kuentzer, Leonardo Rezende Juracy, Matheus T. Moreira, Alexandre M. Amory. 1-6 [doi]
• Energy Aware Demodulation Implementation with Fixed Point Adaptive Precision for OFDM SystemsRobson F. de Moraes, Juraci F. Galdino, Ernesto L. Pinto. 1-6 [doi]
• Push-Pull Based Operational Transconductor Amplifier Topologies for Ultra Low Voltage SuppliesLuis Henrique Rodovalho. 1-6 [doi]
• Low-Power HEVC 1-D IDCT Hardware ArchitectureLuciano A. Braatz, Daniel Palomino, Luciano Volcan Agostini, Bruno Zatt, Marcelo Schiavon Porto. 1-6 [doi]
• Optimization of Single-Stage FFT Architectures Using Multiple Constant MultiplicationJoão G. Nizer Rahmeier, Eduardo A. C. da Costa, Alessandro Girardi, Sidinei Ghissoni. 1-6 [doi]
• A Modular and Distributed Impedance Control Architecture on a Chip for a Robotic HandSergio A. Pertuz, Carlos H. Llanos, Cesar A. Pena, Daniel Munoz. 1-6 [doi]
• A Novel SPICE Model of Memristive Devices with Threshold Current Based ControlCesar de S. Dias, Paulo F. Butzen. 1-6 [doi]
• Ultra Low Power Tunable Filter for a Low Phase Shift on Electrocardiogram QRS-Complex AcquisitionGerman Fierro, Fernando Silveira. 1-5 [doi]
• Extracting Packet Dependence from NoC Simulation Traces Using Association Rule MiningWeslley N. Costa, Lucas P. Lima, Otávio Alcântara de Lima Jr.. 1-6 [doi]
• Exploring Asynchronous End-to-End Communication Through a Synchronous NoCIacana I. Weber, Fernando Gehm Moraes, Leonardo L. de Oliveira, Everton Alceu Carara. 1-6 [doi]
• 3D-HEVC DMM-1 Parallelism Exploration Targeting Multicore SystemsGustavo Sanchez, Luciano Luciano Agostini, Leonel Sousa, César A. M. Marcon. 1-5 [doi]
• Evaluation of Compiler Optimization Flags Effects on Soft Error ResiliencyGuilherme E. Medeiros, Felipe T. Bortolon, Ricardo Reis, Luciano Ost. 1-6 [doi]
• Design of an RF Six-Mode CMOS Power Amplifier for Efficiency Improvement at Power BackoffB. Tarui, F. Santos, E. L. Santos, Bernardo Leite, André A. Mariano. 1-6 [doi]
• Fault-Tolerance at the Management Level in Many-Core SystemsVinicius Fochi, Luciano L. Caimi, Marcelo H. da Silva, Fernando Gehm Moraes. 1-6 [doi]
• A Distributed Functional Verification Environment for the Design of System-on-Chip in Heterogeneous ArchitecturesThiago Werlley B. Silva, Daniel C. Morais, Halamo G. R. Andrade, Felipe C. A. Nunes, Elmar Uwe Kurt Melcher, Antonio Marcus Nogueira de Lima, Alisson V. Brito. 4849-4854 [doi]