Table of Contents

• LMS-based adaptive temperature prediction scheme for proactive thermal-aware three-dimensional Network-on-Chip systemsKun-Chih Chen, Huai-Ting Li, An-Yeu Andy Wu. 1-4 [doi]
• Dark Silicon - A thermal perspectiveJörg Henkel. 1 [doi]
• Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systemsJanak Porwal, Sanket Diwale, Vinay B. Y. Kumar, Sachin B. Patkar. 1-4 [doi]
• A 22.4 fJ/conversion 0.7V 1.6μW 10-bit successive approximation ADCMeng-Lieh Sheu, Te-Hsiang Liu, Lin-Jie Tsao. 1-4 [doi]
• Oscillation-based diagnosis by using harmonics analysis on analog filtersYanbing Wang, Hong Wang, Deyong Meng, Bingqin Zhou. 1-4 [doi]
• TM/3D ICsSandeep Kumar Goel, Min-Jer Wang, Saman Adham, Ashok Mehta, Frank Lee. 1-4 [doi]
• Power-switch routing for reducing dynamic IR drop in multi-domain MTCMOS designsYi-Ming Wang, Mango Chia-Tso Chao, Shi-Hao Chen, Hung-Chun Li. 1-4 [doi]
• Thermal-aware Dynamic Buffer Allocation for Proactive routing algorithm on 3D Network-on-Chip systemsYuan-Sheng Lee, Hsien-Kai Hsin, Kun-Chih Chen, En-Jui Chang, An-Yeu Andy Wu. 1-4 [doi]
• An all-digital phase-locked loop compiler with liberty timing filesChing-Che Chung, Duo Sheng, Chen-Han Chen. 1-4 [doi]
• A novel power noise simulation methodology for chip design using Wafer Level Chip Scale PackagingYipin Wu, Zhigang Hao, Jingchun Han, Joy Tsai. 1-4 [doi]
• All-digital delay-locked loop for 3D-IC die-to-die clock synchronizationChing-Che Chung, Chi-Yu Hou. 1-4 [doi]
• A 1.5GHz all-digital frequency-locked loop with 1-bit ΔΣ frequency detection in 0.18μm CMOSHuiying Zhuo, Yu Li, Woogeun Rhee, Zhihua Wang. 1-4 [doi]
• SAT-based complete logic implication with application to logic optimizationYung-Chih Chen, Kung-Ming Ji. 1-4 [doi]
• Electroceuticals - Replacing drugs by devices enabled through advanced VLSI technologiesDavid Prutchi. 1 [doi]
• Event-driven read-out circuits for energy-efficient sensor-SoC'sChen-Yi Lee, Kelvin Yi-Tse Lai, Shu-Yu Hsu. 1-2 [doi]
• Bias adapted operation of CMOS PA for handset applicationBumman Kim. 1 [doi]
• A 3.5-4GHz FMCW radar transceiver design with phase-domain oversampled ranging by utilizing a 1-bit ΔΣ TDCWei Zhang, Yizhi Han, Fei Chen, Bo Zhou, Xican Chen, Woogeun Rhee, Zhihua Wang. 1-4 [doi]
• Energy efficiency in the Internet of Things - Critical or nice-to-have?Yen-Kuang Chen. 1 [doi]
• Precision material engineering - An equipment point of viewMei Chang. 1-3 [doi]
• Complexity-effective implementation of programmable FIR filters using simplified canonic signed digit multiplierKuo-Chiang Chang, Ching-Hao Lin, Chih-Wei Liu. 1-4 [doi]
• Next generation front end solutions for mobile applicationEddie Spears. 1 [doi]
• Thermal challenges to building reliable embedded systemsZebo Peng. 1-2 [doi]
• A low-area digitalized channel selection filter for DSRC systemHung-Wen Lin, Jin-Yi Lin, Min-Tai Chuang. 1-4 [doi]
• A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stageTsu-Wei Tseng, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai. 1-4 [doi]
• Apply high-level synthesis design and verification methodology on floating-point unit implementationChia-I. Chen, Chin-Yeh Yu, Yen-Ju Lu, Chi-Feng Wu. 1-4 [doi]
• Internet of Things: Connecting the physical and digital worldsDipesh Patel. 1 [doi]
• Roadway to innovationRonald M. Martino. 1 [doi]
• A hardware-friendly method for rate-distortion optimization of HEVC intra codingWeiwei Shen, Yibo Fan, Leilei Huang, Jiali Li, Xiaoyang Zeng. 1-4 [doi]
• Trends and directions in networking - Impact of virtualization and cloudAtul Tambe. 1 [doi]
• A frequency-domain detection and estimation scheme for single-tone interference suppressionHung-Chin Wang. 1-4 [doi]
• A 40-MHz current-mode hysteretic controlled switching converter with digital push-pull current pumping technique for high performance microprocessorsJoseph Sankman, Minkyu Song, Dongsheng Ma. 1-4 [doi]
• Optimized stacking order for 3D-stacked ICs considering the probability and cost of failed bondingChang Hao, Huaguo Liang, Li Yang, Yiming Ouyang. 1-4 [doi]
• A passive supply-resonance suppression filter utilizing inductance-enhanced coupled bonding-wire coilsTaisuke Hayashi, Noriyuki Miura, Kumpei Yoshikawa, Makoto Nagata. 1-4 [doi]
• Power integrity optimization on USB power distribution network for EMI reductionKuo-Chiang Hung, Tim Chen. 1-4 [doi]
• A novel DFT architecture for 3DIC test, diagnosis and repairMincent Lee, Saman Adham, Min-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Hao Chen. 1-4 [doi]
• A fast transient and under/overshoot suppression DC-DC Buck converter with ACP controlJing-Teng Lin, Jiunn-Hung Shiau, Chien-Hung Tsai. 1-4 [doi]
• Characterization and compensation of performance variability using on-chip monitorsIslam A. K. M. Mahfuzul, Hidetoshi Onodera. 1-4 [doi]
• A dual-mode CMOS image sensor for optical wireless communicationChih-Hao Lin, Chih-Cheng Hsieh, Che-Chun Lin, Ren-Jr Chen. 1-4 [doi]
• Low power pipelined SAR ADC with loading-free architectureJia-Jhang Wu, Soon-Jyh Chang, Sheng-Hsiung Lin, Chun-Po Huang, Guan-Ying Huang. 1-4 [doi]
• Output selection for test response compaction based on multiple countersWei-Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong-Yu Hsieh. 1-4 [doi]
• A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bitsRong-Zhou Kuo, Hao-Chiao Hong. 1-4 [doi]
• Two-staged parallel layer-aware partitioning for 3D designsYi-Hang Chen, Yi-Ting Chen, Juinn-Dar Huang. 1-4 [doi]
• A 1V 10-bit 500KS/s energy-efficient SAR ADC using Master-Slave DAC technique in 180nm CMOSYi-Long Yu, Fu-Chen Huang, Chorng-Kuang Wang. 1-4 [doi]
• Assessing automotive functional safety microprocessor with ISO 26262 hardware requirementsYung-Chang Chang, Li-Ren Huang, Hsing-Chuang Liu, Chih-Jen Yang, Ching-Te Chiu. 1-4 [doi]
• C3Map and ARPSO based mapping algorithms for energy-efficient regular 3-D NoC architecturesKartikeya Bhardwaj, Pravin S. Mane. 1-4 [doi]
• Analog front-end amplifier for ECG applications with feed-forward EOS cancellationChih-Chan Tu, Tsung-Hsien Lin. 1-4 [doi]
• An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programmingShih-Hsin Hsu, Wei-Zen Chen, Jui-Pin Zheng, Sean S.-Y. Liu, Po-Cheng Pan, Hung-Ming Chen. 1-4 [doi]
• Design of low-cost elliptic curve cryptographic engines for ubiquitous securityHsin-Yu Ting, Chih-Tsun Huang. 1-4 [doi]
• A survey of technical trend of ADAS and autonomous drivingRyosuke Okuda, Yuki Kajiwara, Kazuaki Terashima. 1-4 [doi]
• An ultra-low-power adaptive-body-bias control for subthreshold circuitsShien-Chun Luo, Chi-Ray Huang, Lih-Yih Chiou. 1-4 [doi]
• An FPGA implementation of high-throughput key-value store using Bloom filterJae Min Cho, Kiyoung Choi. 1-4 [doi]
• Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisitionShang-Lin Wu, Po-Tsang Huang, Teng-chieh Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang. 1-4 [doi]
• Low-complexity architecture for Chase soft-decision Reed-Solomon decodingYung-Kuei Lu, Shen-Ming Chung, Ming-Der Shieh. 1-4 [doi]
• SiGe BiCMOS technology and circuits for active safety systemsFranz Dielacher, Marc Tiebout, Rudolf Lachner, Herbert Knapp, Klaus Aufinger, Willy Sansen. 1-4 [doi]
• Smart feature detection device for cloud based video recognition systemTakeshi Ikenaga, Takahiro Suzuki. 1-3 [doi]
• A 360-degree panoramic video system designKai-Chen Huang, Po-Yu Chien, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo. 1-4 [doi]
• Will reliability limit Moore's law?Anthony S. Oates. 1 [doi]
• On efficient error-tolerability evaluation and maximization for image processing applicationsTong-Yu Hsieh, Kuan-Hsien Li, Yi-Han Peng. 1-4 [doi]
• An effective arterial blood pressure signal processing system based on EEMD methodShang-Yi Chuang, Jia-Ju Liao, Chia-Ching Chou, Chia-Chi Chang, Wai-Chi Fang. 1-4 [doi]
• A novel abstraction-guided simulation approach using posterior probabilities for verificationJian Wang, Huawei Li, Xiaowei Li 0001. 1-4 [doi]
• Triangle-based process hotspot classification with dummification in EUVLPo-Hsun Wu, Che-Wen Chen, Chi-Ruo Wu, Tsung-Yi Ho. 1-4 [doi]
• Low complexity stereo matching algorithm using adaptive sized square windowDer-Wei Yang, Li-Chia Chu, Chun-Wei Chen, Jia-Ming Gan, Jonas Wang, Ming-Der Shieh. 1-4 [doi]
• Advanced CMOS reliability challengesChetan Prasad. 1-2 [doi]
• The resilience wall: Cross-layer solution strategiesSubhasish Mitra, Pradip Bose, Eric Cheng, Chen-Yong Cher, Hyungmin Cho, Rajiv V. Joshi, Young Moon Kim, Charles R. Lefurgy, Yanjing Li, Kenneth P. Rodbell, Kevin Skadron, James H. Stathis, Lukasz G. Szafaryn. 1-11 [doi]
• Accelerated domain decomposition FEM-BEM solver for magnetic resonance imaging (MRI) via discrete empirical interpolation methodNiloofar Farnoosh, Athanasios G. Polimeridis, Thomas J. Klemas, Luca Daniel. 1-4 [doi]
• An integrated boost converter with maximum power point tracking for solar photovoltaic energy harvestingSung-Yao Wang, Hung-Hsien Wu, Chia-Ling Wei. 1-4 [doi]
• Efficient test length reduction techniques for interposer-based 2.5D ICsShyue-Kung Lu, Huai-Min Li, Masaki Hashizume, Jin-Hua Hong, Zheng-Ru Tsai. 1-4 [doi]
• SOI technology: An opportunity for RF designers?Jean-Pierre Raskin. 1-2 [doi]
• Practical electrical parameter aware methodology for analog designers with emphasis on LDE aware for devicesHau-Yung Chen, Ming Juan, Hsin-Hao Chen, Arvin Guan. 1-4 [doi]
• Full system simulation framework for integrated CPU/GPU architecturePo-Han Wang, Gen-Hong Liu, Jen-Chieh Yeh, Tse Min Chen, Hsu-Yao Huang, Chia-Lin Yang, Shih-Lien Liu, James Greensky. 1-4 [doi]
• Simultaneous optimization for low dropout regulator and its error amplifier with process variationYen-Lung Chen, Guan-Ming Chu, Ying-Chi Lien, Ching-Mao Lee, Chien-Nan Jimmy Liu. 1-4 [doi]
• VLSI implementations of stereo matching using Dynamic ProgrammingShen-Fu Hsiao, Wen-Ling Wang, Po-Sheng Wu. 1-4 [doi]
• Keep-Out-Zone analysis for three-dimensional ICsMostafa Said, Mohamed El-Sayed, Farhad Mehdipour, Nobuaki Miyakawa. 1-4 [doi]
• Design for reliability for low power digital circuitsSriram Kalpat. 1 [doi]
• Highly automated and efficient simulation environment with UVMHung-Yi Yang. 1-3 [doi]
• Skillfully diminishing antenna effect in layer assignment stageChih-Chien Lin, Wen-Hao Liu, Yih-Lang Li. 1-4 [doi]
• Highly integrated 4G front end modules for handset applications - A designer's perspectiveNick Cheng. 1 [doi]
• A mixed-signal phase-domain FSK demodulator for BLE single-path low-IF receiverCuei-Ling Hsieh, Chang-Ming Lai, Guan-Hong Ke, Jenny Yi-Chun Liu, Po-Chiun Huang. 1-4 [doi]
• An all-digital delay-locked loop for high-speed memory interface applicationsShih-Lun Chen, Ming-Jing Ho, Yu-Ming Sun, Maung Wai Lin, Jung-Chin Lai. 1-4 [doi]
• Design trends and test challenges in automotive electronicsLi-C. Wang. 1 [doi]
• A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidthJia-An Jheng, Wei-Sung Chang, Tai-Cheng Lee. 1-4 [doi]
• Scaling trends and challenges of advanced memory technologySeok Hee Lee. 1 [doi]