🙏🙏🙏Sorry!!! My post yesterday about 💰 price comparisons for PICs and CMOS Chips was misleading. I took it off. The comparison was not for the chip price. The comparison was for the price of design space on a multi-project wafer (MPW) run. Here, I make it more explicit. For the #siliconphotonics process, the per mm^2 design space ranges from 💲2K [silicon photonics chip with active and passive photonic functions] to 💲10K [for a monolithic silicon photonics electronic-photonic process flow]. This price is 4❎ to 20❎ more than the price of design space for an InP PIC process. Compared with an advanced CMOS process (12nm and below), #siliconphotonic process design space is 6-15 ❎cheaper than for an advanced CMOS process flow. The design space for #siliconphotonics and electronics is comparable when both use a comparable node. I hope I have not messed things up this time 🙇🙇🙇
Aly Abdou
2mo
Is there any indication about the space needed for a full circuit per technology? E.g., How much space is needed for DWDM transceiver per technology?
Harel Frish
2mo
You mean price per wafer maybe?, if your statment for advanced CMOSnis right, that i lt is $30K/mm^2, is that mean you claimimg a single 300mm wafer on advanced node will cost north of $2m? Please clarify
Nick S.
2mo
Not sure about your figures.
Hmm... InP approximately 10 times the cost compared with SiP? What's the reason for this difference? Mask costs should be more or less equal, I think...
The information is very concise and obviously made from an expert level - for beginners and those who are venturing into this space it might not be easy to interpret--this figure simplifies the comparison of technologies by focusing solely on the cost per space unit, but other factors like performance, scalability, and suitability for specific applications are equally important. I believe a full understanding of the pros and cons of each technology space needs to be present when reading this figure - which further complements the understanding of integration challenges :)
Kévin Cognée
2mo
Is the comparison really relevant? A high-density PIC with active components or detectors will most likely require a flip-chipped ASIC for control/readout, no matter if it is InP or SiPh. However, this ASIC also needs to be designed and fabricated... on CMOS usually.
Nice that you're evolving, not cast in stone.
Research Team Leader and silicon photonics pioneer at VTT
2moThis is an interesting comparison that tells something about the wafer processing costs and especially the costs of the litho mask sets, which are high in advanced CMOS. To be fair, one should note that here the price correlates strongly with the integration density. Advanced CMOS allows to integrate orders of magnitude more funtionalities per area compared to SiPh, which is again more densely integrated than InP. Transistors, SiPh modulators and InP lasers are very different functionalities, so it is impossible to compare the cost per functionality. Still, price per design area is good to know for each technology.